Phase locked loop
AssigneeHynix Semiconductor Inc.
InventorsHae-Rang Choi, Yong-Ju Kim, Jae-Min Jang
Life of this patent
Estimating the term…
Abstract
A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
Claims10
A phase locked loop, comprising:
- a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result;
- an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result;
- a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result;
- and
- an oscillator configured to generate an output clock in response to the frequency control signal,
- wherein the initial frequency value provider detects the frequency of the input clock by detecting a logic value of the input clock at rising edges of first to Nth delay signals, where N is any positive integer, and the first to Nth delay signals are obtained by sequentially delaying a sampling reference signal by a first delay value.
A method for operating a phase locked loop, comprising:
- detecting a frequency of an input clock to produce a frequency detection result;
- determining an initial frequency of an output clock based on the frequency detection result;
- comparing a phase of the input clock with a phase of a feedback clock to produce a phase comparison result;
- and
- increasing or decreasing the frequency of the output clock based on the phase comparison result,
- wherein the detecting of the frequency of the input clock comprises:
- generating a plurality of first delay signals by sequentially delaying a sampling reference signal by a first delay value:
- and
- detecting a logic value of the input clock at rising edges of the plurality of the first delay signals.
Dependencies are inferred from the claim text.