US 8,410,835 B1Granted

Leakage tolerant phase locked loop circuit device

AssigneeInternational Business Machines Corporation

InventorsMichael A. Sorna, Pradeep Thiagarajan

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Abstract

Leakage tolerant phase locked loop (PLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant PLL circuit device are provided. Embodiments include a PLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and feedback divider. The secondary correction circuit is configured to generate and provide a secondary error-frequency signal to the error controller. The secondary correction circuit is configured to generate the secondary error-frequency signal in response to detecting a particular edge of a divided VCO output signal. The primary loop is configured to control a frequency adjustment based on at least one of a first error-frequency-increase signal, a first error-frequency-decrease signal, and the secondary error-frequency signal.

Claims20

Dependent claims

A leakage tolerant phase locked loop (PLL) circuit device, the PLL circuit device comprising:

a primary loop configured to generate a feedback signal having a phase that substantially matches a phase of a reference signal, wherein the primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and a feedback divider, wherein the VCO is configured to generate a VCO output signal;
the feedback divider configured to generate the feedback signal based on the VCO output signal, wherein the phase detector is configured to generate one of a first error-frequency-increase signal and a first error-frequency-decrease signal based on a determination of the phase difference between the feedback signal and the reference signal;
a secondary correction circuit configured to generate a secondary error-frequency signal wherein the secondary correction circuit includes an error generator;
and
a secondary correction circuit divider that is configured to generate a divided VCO output signal based on the VCO output signal, wherein the error generator is configured to generate the secondary error-frequency signal in response to detecting a particular edge of the divided VCO output signal, wherein the primary loop is configured to control, based on at least one of the first error-frequency-increase signal, the first error-frequency-decrease signal, and the secondary error-frequency signal, a frequency adjustment provided by the VCO to the VCO output signal.

2 more elements

A method of locking a phase of a feedback signal to a phase of a reference signal using a leakage tolerant phase locked loop (PLL) circuit device, the method comprising:

generating, by a primary loop of the PLL circuit device, the feedback signal having a phase that substantially matches a phase of the reference signal;
wherein the primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and a feedback divider;
generating, by the VCO, a VCO output signal and providing the VCO output signal to the feedback divider;
generating, by the phase detector, one of a first error-frequency-increase signal and a first error-frequency-decrease signal based on a determination of the phase difference between the feedback signal and the reference signal;
generating, by a secondary correction circuit divider coupled between the VCO and a secondary correction circuit, a divided VCO output signal based on the VCO output signal;
generating, by the secondary correction circuit, a pulse of a secondary error-frequency signal in response to detecting a particular edge of the divided VCO output signal;
and
based on at least one of the first error-frequency-increase signal, the first error-frequency-decrease signal, and the secondary error-frequency signal, controlling, by the primary loop, a frequency adjustment provided by the VCO to the VCO output signal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/342,453Filed 3 Jan 2012
Granted: 2 Apr 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03L 7/101
For assuring initial synchronisation or for broadening the capture range: using an additional control signal to the controlled loop oscillator…
H03L 7/0891
The phase or frequency detector generating up-down pulses: the up-down pulses controlling source and sink current generators, e.g. a charge pump
H03L 7/093
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using special…
H03L
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or