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US 8,410,820 B2Granted
High speed latch comparators
AssigneeBroadcom Corporation
InventorsKlaas Bult, Rudy Van de Plassche, Jan Mulder
Life of this patent
Estimating the term…
Abstract
In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
Claims22
A latch circuit, comprising:
- a bistable latch that includes:
- a first bistable latch transistor and a second bistable latch transistor;
- a first port to receive a first input current signal and produce a first output voltage signal;
- and
- a second port to receive a second input current signal and produce a second output voltage signal;
- and
- a second latch separate from the bistable latch and connected to the first port of the bistable latch to provide a feedback signal to the first port based on the first output voltage signal, the second latch including:
- a first latch transistor having a source terminal configured to directly connect to a power supply voltage;
- and
- a second latch transistor having a source terminal directly connected to a ground potential,
- wherein the first port reaches a steady state value based on the first and second input current signals and the feedback signal,
- wherein a source of the first bistable latch transistor is directly connected to the ground potential, and
- wherein a source of the second bistable latch transistor is directly connected to the ground potential.
10 more elements
An analog-to-digital converter, comprising:
- a comparator having a first input to receive an analog signal and a second input to receive a reference signal, the comparator producing a digital signal and including a latch circuit, the latch circuit including:
- a bistable latch that includes:
- a first bistable latch transistor and a second bistable latch transistor;
- a first port to receive a first input current signal and produce a first output voltage signal;
- and
- a second port to receive a second input current signal and produce a second output voltage signal;
- and
- a second latch separate from the bistable latch and connected to the first port of the bistable latch to provide a feedback signal to the first port based On the first output voltage signal, the second latch including:
- a first latch transistor having a source terminal configured to directly connect to a power supply voltage;
- and
- a second latch transistor having a source terminal directly connected to a ground potential,
- wherein the first port reaches a steady state value based on tie first and second input current signals and the feedback signal,
- wherein a source of the first bistable latch transistor is directly connected to the ground potential, and
- wherein a source of the second bistable latch transistor is directly connected to the ground potential.
11 more elements
A flash analog-to-digital converter, comprising:
- a voltage ladder to provide a plurality of reference voltages;
- an input stage to produce a differential current signal associated with each of the plurality of reference voltages and an input analog signal, each differential current signal including first and second input current signals;
- and
- a plurality of latch comparators each receiving the first and second input current signals and producing a digital output signal, each latch comparator including:
- a bistable latch that includes:
- a first bistable latch transistor and a second bistable latch transistor;
- a first port to receive the first input current signal and produce a first output voltage signal;
- and
- a second port to receive a second input current signal and produce a second output voltage signal;
- and
- a second latch separate from the bistable latch and connected to the first port of the bistable latch to provide a feedback signal to the first port based on the first output voltage signal, the second latch including:
- a first latch transistor having a source terminal configured to directly connect to a power supply voltage;
- and
- a second latch transistor having a source terminal directly connected to a ground potential;
- wherein the first port reaches a steady state value based on the first and second input current signals and the feedback signal,
- wherein a source of the first bistable latch transistor is directly connected to the ground potential, and
- wherein a source of the second bistable latch transistor is directly connected to the ground potential.
14 more elements
A latch circuit, comprising:
- a bistable latch that includes:
- a first port to receive a first input current signal and produce a first output voltage signal;
- and
- a second port to receive a second input current signal and produce a second output voltage signal;
- and
- a first bistable latch transistor having a gate terminal and a source terminal;
- and
- a second bistable latch transistor having a gate terminal and a source terminal,
- the source terminal of the first bistable latch transistor being directly connected to the source terminal of the second bistable latch transistor, each of the source terminal of the first bistable latch transistor and the source terminal of the second bistable latch transistor being directly connected to the ground potential,
- the gate terminal of the first bistable latch transistor being directly connected to the second port, and
- the gate terminal of the second bistable latch transistor being directly connected to the first port;
- and
- a second latch separate from the bistable latch and connected to the first port of the bistable latch to provide a feedback signal to the first port based on the first output voltage signal, the second latch including:
- a first latch transistor having a source terminal configured to directly connect to a power supply voltage;
- and
- a second latch transistor having a source terminal directly connected to a ground potential,
- wherein the first port reaches a steady state value based on the first and second input current signals and the feedback signal.
14 more elements
Dependencies are inferred from the claim text.