Programmable pulse width discriminator
AssigneeSTMicroelectronics S.r.l.
InventorVincent Himpe
Life of this patent
Estimating the term…
Abstract
Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.
Claims30
A pulse width discriminator circuit operable to sample an input signal and produce an output signal, the pulse width discriminator circuit comprising:
- a first multiplexer operable to receive an input signal and load a first value in a first memory when said input signal is a first logic state, and load a second value in said first memory when said input signal is a second logic state, wherein said loaded value is stored in said first memory responsive to a clock signal;
- a first comparator operable to compare said stored first memory value to said second value;
- a second memory operable to receive said stored first memory value and, responsive to said clock signal, store said stored first memory value when said stored first memory value is greater than said second value and said input signal is said second logic state;
- a second comparator operable to compare said stored second memory value to a first threshold value and output a second comparator signal having a third logic state or a fourth logic state;
- a third comparator operable to compare said stored second memory value to a second threshold value and output a third comparator signal having a fifth logic state and a sixth logic state;
- and
- logic circuitry operable to generate an output signal indicative of a relationship between said stored second memory value and at least one of said first and second threshold values.
An apparatus comprising:
- first circuitry operable to sample an input signal and count the number of consecutive samples for which the input signal is a first logic state, said first circuitry further operable to store said number of consecutive samples in a memory when said input signal changes from said first logic state to a second logic state;
- and
- second circuitry operable to compare said number of consecutive samples to first and second threshold values and produce a first output signal having a third logic state when said number of consecutive samples is less than said first threshold value and having a fourth logic state when said number of consecutive samples is greater than or equal to said first threshold value, produce a second output signal having a fifth logic state when said number of consecutive samples is greater than said second threshold value and having a sixth logic state when said number of consecutive samples is less than or equal to said second threshold value, and produce a third output signal having a seventh logic state when said number of consecutive samples is between said first and second threshold values and an eighth logic state when said number of consecutive samples is not between said first and second threshold values.
A method for evaluating a measured pulse width of a sampled input signal, the method comprising:
- sampling an input signal;
- counting the number of consecutive samples for which the input signal is a first logic state;
- comparing the number of consecutive samples to a first threshold value and producing a first comparison signal;
- comparing the number of consecutive samples to a second threshold value and producing a second comparison signal;
- comparing the first comparison signal to the second comparison signal and producing a third comparison signal;
- receiving a first control signal and a second control signal;
- outputting said third comparison signal when said first control signal is a second logic state;
- outputting said first comparison signal when said first control signal is a third logic state and said second control signal is a fourth logic state;
- and
- outputting said second comparison signal when said first control signal is said third logic state and said second control signal is a fifth logic state.
Dependencies are inferred from the claim text.