Receiver circuits for differential and single-ended signals

An integrated circuit comprising:

• a plurality of receiver circuits, wherein each of the plurality of receiver circuits is capable of receiving a differential signal and a single-ended signal, and wherein each of the plurality of receiver circuits includes:
• a first amplifier configured to receive the differential signal at a first input and a second input in response to a selection of a differential mode of operation;
• and
• a second amplifier coupled to the first amplifier, wherein the second amplifier is configured to receive a reference signal at a third input and a single-ended signal at the first input in response to a selection of a single-ended mode of operation, wherein the first input is shared by the second amplifier and the first amplifier, wherein the differential signal received by a first receiver circuit of the plurality of receiver circuits is a clock signal and the single-ended signal received by a second receiver circuit of the plurality of receiver circuits is a data signal referenced to the clock signal.

A method comprising:

• providing a receiver circuit including:
• a differential amplifier configured to receive a first signal of a differential pair of signals at a first input and a second signal of the differential pair of signals at a second input in response to a selection of a differential mode of operation;
• a first inverter circuit coupled to an output of the differential amplifier;
• a second amplifier coupled to the differential amplifier, wherein the second amplifier is configured to receive a reference signal at a third input and a single-ended signal at the first input in response to a selection of a single-ended mode of operation, and wherein the second amplifier is configured, in the differential mode, to provide current flow through a transistor having a gate coupled to receive the reference signal, the current passing through a current source used by the differential amplifier;
• and
• a second inverter coupled to an output of the second amplifier;
• and
• setting a beta ratio of at least one of the first or second inverter circuits to adjust a delay of at least one of the differential pair of signals or the single-ended signal.

In a circuit having a plurality of receiver circuits, each of the plurality of receiver circuits including a differential amplifier and a single-ended amplifier, wherein each of the plurality of receiver circuits includes a first transistor having a gate terminal coupled to receive a first signal, and wherein the first transistor is shared between the differential amplifier and the single-ended amplifier, a method comprising:

• configuring a first receiver circuit of the plurality of receiver circuits for differential operation, wherein the first signal is one of a differential pair representing the input to the first receiver circuit;
• the single-ended amplifier in the first receiver circuit providing current, in differential operation, through a transistor having a gate coupled to receive a reference voltage for single-ended operation, the current passing through a current source used by the differential amplifier;
• configuring a second receiver circuit of the plurality of receiver circuits for single-ended mode, wherein the first signal is the single-ended input to the second receiver circuit and the second receiver circuit is further coupled to receive the reference voltage to which the single-ended input is referenced;
• wherein a first delay of the differential pair through the first receiver circuit is approximately the same as a second delay of the single-ended input through the second receiver circuit.

An integrated circuit comprising:

• a plurality of receiver circuits, wherein each of the plurality of receiver circuits is capable of receiving a differential signal and a single-ended signal, and wherein each of the plurality of receiver circuits includes:
• a first amplifier configured to receive the differential signal at a first input and a second input in response to a selection of a differential mode of operation;
• and
• a second amplifier coupled to the first amplifier, wherein the second amplifier is configured to receive a reference signal at a third input and a single-ended signal at the first input in response to a selection of a single-ended mode of operation, wherein the first input is shared by the second amplifier and the first amplifier, wherein the differential signal received by a first receiver circuit of the plurality of receiver circuits is a data signal and the single-ended signal received by a second receiver circuit of the plurality of receiver circuits is a clock signal to which the data signal is referenced.