Bias circuit generating bias from supply and threshold voltages

An output driver compensated for process, voltage, and temperature variations, comprising:

• a first detection circuit configured to generate a first characterization voltage that represents a variation of a power supply voltage from a nominal voltage;
• a second detection circuit configured to generate a second characterization voltage that represents a threshold voltage of at least one p-type transistor;
• a third detection circuit configured to generate a third characterization voltage that represents a threshold voltage of at least one n-type transistor;
• a summing circuit coupled to the first, second, and third detection circuits and configured to generate the bias voltage, wherein the bias voltage is the power supply voltage reduced by a weighted sum of the first, second, and third characterization voltages;
• and
• a driver circuit including at least two p-type transistors coupled in series, the at least two p-type transistors configured to drive an output signal to the power supply voltage in response to the bias voltage being applied to a respective gate of each of the at least two p-type transistors.

A bias circuit that generates a bias voltage, comprising:

• a first detection circuit configured to generate a first characterization voltage from a first, a second, and a third n-type transistor coupled in series between a power supply signal and ground, wherein:
• the power supply signal is coupled to a gate of the first n-type transistor,
• a first fraction of a power supply voltage of the power supply signal is applied to a gate of the second n-type transistor, and
• a second fraction of the power supply voltage is applied to a gate of the third n-type transistor;
• a second detection circuit configured to generate a second characterization voltage from a first p-type transistor and at least one second p-type transistor coupled in series between an auxiliary power supply signal and ground, wherein:
• the auxiliary power supply signal is coupled to a gate of the first p-type transistor, and
• each of the at least one second p-type transistor is diode connected;
• a third detection circuit configured to generate a third characterization voltage from a third p-type transistor and at least one fourth n-type transistor coupled in series between the auxiliary power supply signal and ground, wherein:
• the auxiliary power supply signal is coupled to a gate of the third p-type transistor, and
• each of the at least one fourth n-type transistor is diode connected;
• and
• a summing circuit configured to generate the bias voltage from a fifth and a sixth n-type transistor and a parallel combination coupled in series between the power supply signal and ground, wherein:
• the power supply signal is coupled to a gate of the fifth transistor,
• the second fraction of the power supply voltage is applied to a gate of the sixth transistor, and
• the first, second, and third characterization voltages are respectively applied to a respective gate of a seventh, an eighth, and a ninth n-type transistor of the parallel combination.