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US 8,410,617 B2Granted
Three dimensional structure memory
AssigneeElm Technology Corporation
InventorGlenn J. Leedy
Life of this patent
Estimating the term…
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
Claims62
An integrated circuit structure comprising:
- a first substrate comprising a first surface having interconnect contacts;
- a second substrate comprising a first surface having interconnect contacts;
- and
- a bond layer between the first surface of the first substrate and the first surface of the second substrate, comprising:
- a plurality of bonds formed from the interconnect contacts of the first surfaces of the first and second substrates and forming portions of signal paths between the first surface of the second substrate and the first surface of the first substrate;
- and,
- at least one bond formed between the first surfaces of the first and second substrates and not forming portions of a signal path between the first surfaces of the first and second substrates, wherein at least one of the first substrate and second substrate is substantially flexible and at least one of the first substrate and the second substrate is and formed from a semiconductor wafer or portion thereof;
- and
- at least one conductive path that passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said at least one of said first and second substrates, wherein the insulation material comprises a low stress dielectric material having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon.
6 more elements
An integrated circuit structure comprising:
- a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate has interconnect contacts;
- a second substrate having topside and bottomside surfaces, wherein the bottomside surface of the second substrate has interconnect contacts;
- and
- a bond layer between the topside surface of the first substrate and the bottomside surface of the second substrates, comprising:
- a plurality of bonds formed from the interconnect contacts forming conductive paths between the topside of the first substrate and the bottomside of the second substrate;
- and,
- at least one bond formed between the topside of the first substrate and the bottomside of the second substrate forming at least one:
- of a non-conductive contact;
- and a conductive contact not formed from one of said interconnect contacts;
- wherein at least one of the first substrate and the second substrate is substantially flexible and at least one of the first and second substrates is and formed from a semiconductor wafer or portion therof;
- and
- at least one conductive path that passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said at least one of said first and second substrates, wherein the insulation material comprises a low stress dielectric material having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon.
9 more elements
An integrated circuit structure comprising:
- a first substrate having a first and second surface;
- a second substrate having a first and second surface, wherein said second surfaces of the first and second substrates are opposite to said first surfaces;
- a plurality of bonded contacts between the first surface of the first substrate and the first surface of the second substrate;
- wherein at least one of said contacts is a signal path conductive contact and at least another one of said contacts is one of:
- a signal path conductive contact;
- a non-signal path conductive contact;
- and a non-conductive contact;
- wherein at least one of the first substrate and second substrate is substantially flexible and at least one of the first substrate and the second substrate is and formed from a semiconductor wafer or portion thereof;
- and
- at least one conductive path that passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said at least one of said first and second substrates, wherein the insulation material comprises a low stress dielectric material having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon.
7 more elements
Dependencies are inferred from the claim text.