3D polysilicon diode with low contact resistance and method for forming same

A method of forming a 3-D memory array comprising:

• forming a first conductive line over a substrate;
• forming a first p-i-n diode over the first conductive line, the forming a first p-i-n diode including the following steps:
• forming a first region of silicon that is doped with a first material having a first conductivity;
• forming a second region of silicon over the first region, the second region is not intentionally doped;
• forming a third region of silicon over the second region;
• doping the third region with a second material having a second conductivity that is opposite from the first conductivity;
• and
• forming a region of SiGe over the third region of silicon;
• forming a second conductive line over the first p-i-n diode;
• forming a second p-i-n diode over the second conductive line, the forming second p-i-n diode including the following steps:
• forming a fourth region of silicon that is doped with a material having the second conductivity;
• forming a fifth region of silicon over the fourth region;
• and
• forming a sixth region of silicon that is doped with a material having the first conductivity over the fifth region;
• and
• forming a third conductive line over the second p-i-n diode.

A three-dimensional memory array comprising:

• a first conductive line;
• a second conductive line;
• a third conductive line;
• a first semiconductor diode that is coupled between the first conductive line and the second conductive line, the first semiconductor diode comprising:
• a first region of silicon, the first region of silicon is doped with a first material having a first conductivity;
• a second region of silicon that is not intentionally doped;
• a third region of silicon, the third region is doped with a second material having a second conductivity that is opposite the first conductivity, the second region is between the first region and the third region;
• and
• a region that includes SiGe adjacent to the third region;
• a first conductive contact between the SiGe region and the second conductive line;
• and
• a second semiconductor diode that is coupled between the second conductive line and the third conductive line, the second semiconductor diode comprising:
• a first region of silicon that is doped with a material having the second conductivity;
• a second region of silicon that is not intentionally doped;
• and
• a third region of silicon that is doped with a material having the first conductivity, the second region of the second semiconductor diode is between the first region and the third region of the second semiconductor diode;
• and
• a second conductive contact that forms a contact between the third region of silicon of the second semiconductor diode and the third conductive line.