CMOSFET device with controlled threshold voltage and method of fabricating the same
AssigneeInstitute of Microelectronics, Chinese Academy of Sciences
InventorsWenwu Wang, Huilong Zhu, Shijie Chen, Dapeng Chen
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Abstract
There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.
Claims12
A Complementary Metal-Oxide-Semiconductor Field Effect Transistor (CMOSFET) device, comprising:
- a semiconductor substrate;
- an interface layer grown on the semiconductor substrate;
- a first high-k gate dielectric layer deposited on the interface layer;
- a metal layer deposited on the first high-k gate dielectric layer;
- a second high-k gate dielectric layer deposited on the metal layer;
- and
- a gate electrode layer deposited on the second high-k gate dielectric layer;
- wherein the metal lager is configured to generate positive or negative charges in the high- k Rate dielectric layers and also interface dipoles between the first high-k gate dielectric lager and interface layer;
- and
- wherein for a N-type Metal Oxide Semiconductor (NMOS) device and a P-type Metal Oxide Semiconductor (PMOS) device, the materials for the metal layer are different, wherein for the NMOS device, the materials for the metal layer comprises any one of rare earth metal Y, La, Dy and Gd, and for the PMOS device, the materials for the metal layer comprises any one of metals Al, Mg and Hf.
A method of fabricating a Complementary Metal-Oxide-Semiconductor Field Effect Transistor (CMOSFET) device, comprising:
- growing an interface layer on a semiconductor substrate;
- depositing a first high-k gate dielectric layer, a metal layer, and a second high-k Rate dielectric layer sequentially on the interface layer to form a stacked structure of the first high-k gate dielectric layer, the metal lager and the second high-k gate dielectric lager, so that the metal layer generates positive or negative charges in the high-k gate dielectric layers and also interface dipoles between the first high-k gate dielectric layer and interface layer
- depositing a gate electrode layer on the stacked structure of the first high-k gate dielectric layer, the metal layer and the second high-k gate dielectric layer to form a gate stack;
- further completing the CMOSFET device based on the gate stack;
- and
- wherein for a N-type Metal Oxide Semiconductor (NMOS) device and a P-type Metal Oxide Semiconductor (PMOS) device, the materials for the metal layer are different, wherein for the NMOS device, the materials for the metal layer comprises any one of rare earth metal Y, La, D and Gd, and for the PMOS device, the materials for the metal layer comprises any one of metals Al, Mg and Hf.
Dependencies are inferred from the claim text.