Method, structure and design structure for customizing history effects of SOI circuits
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Edward J. Nowak
Life of this patent
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Abstract
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.
Claims10
A structure, comprising:
- a high-leakage dielectric formed in a divot on each of sides of a segmented field effect transistor (FET) comprised of active silicon islands and gate electrodes thereon;
- a low-leakage dielectric on and in contact with a surface of the active silicon islands, adjacent the high-leakage dielectric, a top surface of the high-leakage dielectric being at a coplanar level as a top surface of the active silicon islands;
- and
- a gate electrode material between a portion of a shallow trench isolation material and the high-leakage dielectric;
- wherein:
- the high-leakage dielectric is a low-k dielectric;
- the low-leakage dielectric is a high-k dielectric material;
- the gate electrode material is formed directly in contact with the high-leakage dielectric;
- top surfaces of the gate electrode material and the shallow trench isolation material are formed at the coplanar level as the top surfaces of the high-leakage dielectric and the active silicon islands;
- and
- the low-leakage dielectric is formed directly in contact with the high-leakage dielectric;
- the high-leakage dielectric, the low-leakage dielectric, the gate electrode material, and the shallow trench isolation material are formed completely above a buried oxide (BOX) layer;
- the gate electrode material is formed directly in contact with the shallow trench isolation material;
- and
- the gate electrodes are formed directly in contact with the shallow trench isolation material.
A method, comprising:
- forming a low-leakage dielectric on and in contact with each upper surface of active silicon islands of a segmented field effect transistor (FET) comprised of the active silicon islands and gate electrodes formed thereon;
- forming a high-leakage dielectric in a portion of a divot formed in a shallow isolation material adjacent to and in contact with each of sides of the segmented FET, a top surface of the high-leakage dielectric being at a coplanar level as a top surface of the active silicon islands;
- and
- forming a gate electrode material between a portion of a shallow trench isolation material and the high-leakage dielectric,
- wherein:
- the low-leakage dielectric is formed directly in contact with the high-leakage dielectric;
- the high-leakage dielectric is a low-k dielectric;
- the low-leakage dielectric is a high-k dielectric material;
- the gate electrode material is formed directly in contact with the high-leakage dielectric;
- top surfaces of the gate electrode material and the shallow trench isolation material are formed at the coplanar level as the top surfaces of the high-leakage dielectric and the active silicon islands;
- the high-leakage dielectric, the low-leakage dielectric, the gate electrode material, and the shallow trench isolation material are formed completely above a buried oxide (BOX) layer;
- the gate electrode material is formed directly in contact with the shallow trench isolation material;
- and
- the gate electrodes are formed directly in contact with the shallow trench isolation material.
Dependencies are inferred from the claim text.