Semiconductor storage device and manufacturing method thereof
AssigneeRenesas Electronics Corporation
InventorsItaru Yanagi, Toshiyuki Mine, Hirotaka Hamamura, Digh Hisamoto, Yasuhiro Shimamoto
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Abstract
In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
Claims16
A semiconductor storage device, comprising:
- a non-volatile memory having an insulating gate type field-effect transistor causing electric field effect to a surface of a semiconductor substrate from a gate electrode via a gate insulating film formed on a main surface of the semiconductor substrate;
- the gate insulating film including a first insulating film forming a charge retention layer, a second insulating film formed between the first insulating film and the semiconductor substrate, and a third insulating film formed between the first insulating film and the gate electrode;
- and
- the non-volatile memory using, as retention charges for information storage, holes injected into the charge retention layer from the gate electrode via the third insulating film and electrons injected into the charge retention layer from the semiconductor substrate via the second insulating film at a time of applying a positive voltage to the gate electrode,
- wherein the gate electrode includes a first silicon layer formed to be in contact with the gate insulating film and a second silicon layer formed to be separated from the gate insulating film via the first silicon layer and doped with an impurity with a concentration higher than that of the first silicon layer,
- wherein the first silicon layer is a p-type silicon layer, an n-type silicon layer, or a non-doped silicon layer, and the second silicon layer is a p+-type silicon layer, and
- wherein the first insulating film is made of silicon nitride, the second and third insulating films are made of silicon oxide, and a fourth insulating film made of silicon oxynitride is interposed between the first insulting film and the third insulating film.
A semiconductor storage device, comprising:
- a non-volatile memory having an insulating gate type field-effect transistor causing electric field effect to a surface of a semiconductor substrate from a gate electrode via a gate insulating film formed on a main surface of the semiconductor substrate;
- the gate insulating film including a first insulating film forming a charge retention layer, a second insulating film formed between the first insulating film and the semiconductor substrate, and a third insulating film formed between the first insulating film and the gate electrode;
- and
- the non-volatile memory using, as retention charges for information storage, holes injected into the charge retention layer from the gate electrode via the third insulating film and electrons injected into the charge retention layer from the semiconductor substrate via the second insulating film at a time of applying a positive voltage to the gate electrode,
- wherein the gate electrode includes a first silicon layer formed to be in contact with the gate insulating film and a second silicon layer formed to be separated from the gate insulating film via the first silicon layer and doped with an impurity with a concentration higher than that of the first silicon layer,
- wherein the first silicon layer is a p-type silicon layer, an n-type silicon layer, or a non-doped silicon layer, and the second silicon layer is a p+-type silicon layer, and
- wherein a silicon oxide layer, a silicon nitride layer, or a metal layer is interposed between the first silicon layer and the second silicon layer.
Dependencies are inferred from the claim text.