CMOSFET device with controlled threshold voltage characteristics and method of fabricating the same
AssigneeInstitute of Microelectronics, Chinese Academy of Sciences
InventorsWenwu Wang, Huilong Zhu, Shijie Chen, Dapeng Chen
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Abstract
There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.
Claims15
A Complementary Metal-Oxide-Semiconductor Field
- Effect Transistor (CMOSFET) device, comprising:
- a semiconductor substrate;
- an interface layer grown on the semiconductor substrate;
- a first high-k gate dielectric layer deposited on the interface layer;
- a cap layer deposited on the first high-k gate dielectric layer;
- a second high-k gate dielectric layer deposited on a structure formed of the first high-k gate dielectric layer and the cap layer;
- and
- a gate electrode layer deposited on a stack formed of the first high-k gate dielectric layer, the cap layer, and the second high-k gate dielectric layer, wherein the cap layer comprises poly-silicon, amorphous silicon, or SiO2, and interacts with the first and second high-k gate dielectric layers to create interface dipoles to adjust a threshold voltage of the CMOSFET device.
A method of fabricating a Complementary Metal-Oxide-Semiconductor Field Effect Transistor (CMOSFET) device, comprising:
- growing an interface layer on a semiconductor substrate;
- depositing a first high-k gate dielectric layer on the interface layer;
- depositing a cap layer on the first high-k gate dielectric layer;
- depositing a second high-k gate dielectric layer on a structure formed of the first high-k gate dielectric layer and the cap layer;
- and
- depositing a gate electrode layer on a stack formed of the first high-k gate dielectric layer, the cap layer, and the second high-k gate dielectric layer, wherein the cap layer comprises poly-silicon, amorphous silicon, or SiO, and interacts with the first and second high-k gate dielectric layers to create interface dipoles to adjust a threshold voltage of the CMOSFET device.
Dependencies are inferred from the claim text.