Non-volatile memory device including a stacked structure and voltage application portion

A non-volatile memory device comprising:

• a stacked structure including a memory portion, and an electrode stacked with the memory portion and having a surface having a portion facing the memory portion;
• and
• a voltage application portion configured to apply a voltage to the memory portion to cause a change in a resistance in the memory portion to store information,
• the surface including:
• a first region containing a first nonmetallic element and at least one element of a metallic element, Si, Ga, and As, the first region being conductive;
• and
• a plurality of second regions containing a second nonmetallic element and the at least one element of a metallic element, Si, Ga, and As, the second regions having a content ratio of the second nonmetallic element higher than a content ratio of the first nonmetallic element in the first region, a difference in electronegativity between the second nonmetallic element and the at least one element of a metallic element, Si, Ga, and As being greater than a difference in electronegativity between the first nonmetallic element and the at least one element of a metallic element, Si, Ga, and As, and
• a layout of the plurality of second regions having anisotropy.

A non-volatile memory device comprising:

• a stacked structure including a memory portion, and an electrode stacked with the memory portion and having an interface facing the memory portion;
• and
• a voltage application portion configured to apply a voltage to the memory portion to cause a change in a resistance in the memory portion to store information,
• the interface including:
• at least one element of a metallic element, Si, Ga, and As;
• a first nonmetallic element;
• and
• a second nonmetallic element, a difference in electronegativity between the second nonmetallic element and the at least one element of a metallic element, Si, Ga, and As being greater than a difference in electronegativity between the first nonmetallic element and the at least one element of a metallic element, Si, Ga, and As,
• a polarization length being defined as a distance twice as long as a distance between the second nonmetallic element and the at least one element of a metallic element, Si, Ga, and As in a polarization pair being formed of a pair of the second nonmetallic element and the at least one element of a metallic element, Si, Ga, and As adjacent to each other on the interface,
• a polarization pair region being defined as a region containing another polarization pair existing within a range of the polarization length viewed from an end of the polarization pair,
• R (%) being defined as an area ratio of the polarization pair region to the interface,
• the memory portion including an orientation improved region provided above the polarization pair region and having an orientation property higher than an orientation property in other region than the orientation improved region,
• an outer periphery of the orientation improved region in a plane at a distance of T (nm) above from the interface toward the memory portion being located at a distance not less than 4.8T outside of an outer periphery of the polarization pair region on the interface, and
• an area of the orientation improved region in the plane at the distance of T (nm) being not less than {R+(100−R)/2} (%) of an area of the interface.