Nonvolatile semiconductor memory device and method of manufacturing the same
AssigneesSanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
InventorTakashi Hiroshima
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AssigneesSanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
InventorTakashi Hiroshima
Estimating the term…
The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure.
A nonvolatile semiconductor memory device comprising:
A nonvolatile semiconductor memory device comprising:
Dependencies are inferred from the claim text.