US 8,409,957 B2 · Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits

Abstract

A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

Claims20

Dependent claims

A method for forming a three dimensional integrated circuit, the method including:

forming a first source region, a first drain region, and a first gate stack portion on a substrate;
forming a first dielectric layer over the first source region, the first drain region, the first gate stack portion and the substrate;
forming a first conductive interconnect portion in the first dielectric layer the first conductive interconnect portion including vias;
forming a second dielectric layer on the first dielectric layer;
forming a second conductive interconnect portion in the second dielectric layer;
forming a graphene layer on the second dielectric layer;
removing portions of the graphene layer to expose portions of the second dielectric layer;
forming a second source region on the second dielectric layer and a second drain region on the second dielectric layer;
forming a third dielectric layer on the graphene layer;
and
forming a metallic gate material on the third dielectric layer.

8 more elements

Dependencies are inferred from the claim text.

Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits

Life of this patent

Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits

Life of this patent

Abstract

Claims20