Methods of forming transistors, and methods of forming memory arrays

A method of a forming transistors, comprising:

• forming a plurality of spaced-apart fins, each of said fins comprising transistor pillars alternating with dielectric material pillars;
• the transistor pillars comprising semiconductor material;
• each of the transistor pillars having a bottom source/drain segment, a channel segment over the bottom source/drain segment, and a top source/drain segment over the channel segment;
• forming oxide within spaces between the fins, the oxide protecting the bottom source/drain segments of the transistor pillars and leaving the other segments of the transistor pillars exposed;
• forming electrically conductive gate material along the fins and over the oxide;
• the electrically conductive gate material being formed to be along the channel segments of the transistor pillars and to leave the top source/drain segments exposed;
• removing the oxide;
• and
• after removing the oxide, implanting dopant into the bottom source/drain segments.

A method of a forming transistors, comprising:

• forming plurality of spaced-apart fins, each of said fins comprising transistor pillars alternating with dielectric material pillars;
• the transistor pillars comprising semiconductor material;
• each of the transistor pillars having a bottom source/drain segment, a channel segment over the bottom source/drain segment, and a top source/drain segment over the channel segment;
• forming first sacrificial material within spaces between the fins, the first sacrificial material protecting the bottom source/drain segments of the transistor pillars and leaving the other segments of the transistor pillars exposed;
• the first sacrificial material being an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature;
• forming gate material along the fins and over the first sacrificial material;
• the gate material being formed to be along sidewalls of the fins and to extend over upper surfaces of the fins;
• the gate material partially filling the spaces between the fins and thus narrowing the spaces between the fins;
• forming second sacrificial material within the narrowed spaces between the fins to fill such narrowed spaces;
• etching back the second sacrificial material and the gate material to expose the top source/drain segments;
• after etching back the second sacrificial material and the gate material, removing the second sacrificial material;
• removing the first sacrificial material;
• and
• implanting dopant into the bottom source/drain segments.

A method of a forming a memory array, comprising:

• forming a plurality of spaced-apart fins, each of said fins comprising transistor pillars alternating with dielectric material pillars;
• each of the vertical transistor pillars comprising a bottom source/drain segment, a channel segment over the bottom source/drain segment, and a top source/drain segment over the channel segment;
• forming oxide within spaces between the fins, the oxide protecting the bottom source/drain segments of the transistor pillars and leaving the other segments of the transistor pillars exposed;
• the oxide etching at a rate of at least about 100 Å/minute with dilute HF at room temperature;
• forming gate material along the fins and over the oxide;
• the gate material being formed to be along the channel segments of the vertical transistor pillars and to leave the top source/drain segment exposed;
• implanting dopant into the bottom source/drain segments, the bottom source/drain segments of individual fins being electrically tied to one another;
• implanting dopant into the top source/drain segments;
• and
• forming bitlines across the top source/drain segments, the fins extending along a first horizontal direction and the bitlines extending along a second horizontal direction which is substantially orthogonal to the first horizontal direction.