US 8,409,947 B2 · Method of manufacturing semiconductor device having stress creating layer

Abstract

Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

Claims9

Dependent claims

A method of forming an integrated circuit device, comprising:

forming an insulated gate electrode of a NMOS transistor on a substrate;
selectively etching the substrate to define source and drain recesses therein;
forming sacrificial stress regions in the source and drain recesses;
then
removing all of the sacrificial stress regions from within the source and drain recesses to thereby expose the source and drain recesses;
and then
forming electrically conductive source and drain plugs in the source and drain recesses, respectively.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/693,080Filed 25 Jan 2010

Priority

KR 10-2009-00080472 Feb 2009

Published

US 2010/0197092 A15 Aug 2010

Granted

2 Apr 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions

Method of manufacturing semiconductor device having stress creating layer

Life of this patent

Method of manufacturing semiconductor device having stress creating layer

Life of this patent

Abstract

Claims9