Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells

A method of forming a field effect transistor, comprising:

• etching a pair of trenches within a semiconductor substrate on opposing sides of a semiconductor material channel region along a length of the channel region;
• etching the semiconductor material bases to form a bulbous lower portion of each trench, each of the bulbous lower portions comprising projections extending laterally outward relative to sidewalls of the trench, a projection of each bulbous lower portion opposing and extending toward a projection of the other bulbous lower portion;
• etching through floors of the bulbous lower portions to extend the pair of trenches deeper within the semiconductor substrate;
• after extending the pair of trenches, filling remaining volume of the trenches with insulative material;
• after said filling, etching the insulative material to expose opposing sides of the semiconductor material along the channel length;
• etching the exposed opposing sides of the semiconductor material along the channel length forming an upwardly projecting channel fin;
• and
• forming a gate over a top and opposing sides of the fin along the channel length.

A plurality of field effect transistors wherein individual of the field effect transistors of the plurality comprise:

• a bulk semiconductor substrate comprising a pair of source/drain regions having a fin channel region received therebetween;
• the fin channel region comprising a channel length extending between the pair of source/drain regions, opposing channel sides extending along the length of the channel region, and a top extending along the length of the channel region;
• a gate received over the fin channel top and the fin channel sides along the channel length;
• and
• trench isolation received within the bulk semiconductor substrate elevationally lower than the fin channel region and beneath the gate, said trench isolation extending along the opposing channel sides along the channel length, the trench isolation in cross section transverse the channel length comprising a lower trench stem and upper transverse projections, the upper transverse projections extending from the stem transversally towards and elevationally lower than the fin channel and the gate.

DRAM circuitry comprising a plurality of individual memory cells wherein individual of the memory cells comprise a field effect transistor having a pair of source/drain regions, a capacitor connected with one of the source/drain regions, and a bit line contact connected with another of the source/drain regions, the field effect transistor comprising:

• a semiconductor substrate comprising the pair of source/drain regions and having a fin channel region received between the pair of source/drain regions;
• the fin channel region comprising a channel length extending between the pair of source/drain regions, opposing channel sides extending along the length of the channel region, and a top extending along the length of the channel region;
• the fin channel region having a maximum thickness transverse the channel length;
• a gate received over the fin channel top and the fin channel sides along the channel length;
• and
• insulative material received immediately beneath the fin channel region and beneath the gate, such insulative material beneath the fin channel region and beneath the gate extending along the channel length and extending only partially across the fin channel maximum thickness transverse the channel length, such insulative material beneath the fin channel region and beneath the gate including opposing portions projecting inwardly toward one another beneath the fin channel region relative to the fin channel region maximum thickness and beneath the gate along the channel length.

DRAM circuitry comprising a plurality of individual memory cells wherein individual of the memory cells comprise a field effect transistor having a pair of source/drain regions, a capacitor connected with one of the source/drain regions, and a bit line contact connected with another of the source/drain regions, the field effect transistor comprising:

• a bulk semiconductor substrate comprising the pair of source/drain regions and having a fin channel region received between the source/drain regions;
• the fin channel region comprising a channel length extending between the pair of source/drain regions, opposing channel sides extending along the length of the channel region, and a top extending along the length of the channel region;
• a gate received over the fin channel top and the fin channel sides along the channel length;
• and
• trench isolation received within the bulk semiconductor substrate elevationally lower than the fin channel region and beneath the gate, said trench isolation extending along the opposing channel sides along the channel length, the trench isolation in cross section transverse the channel length comprising a lower trench stem and upper transverse projections, the upper transverse projections extending from the stem transversally towards and elevationally lower than the fin channel and the gate.