Process of forming an electronic device including a nonvolatile memory cell having a floating gate electrode or a conductive member with different portions

A process of forming an electronic device including a nonvolatile memory cell comprising:

• forming a field isolation region within a substrate to define first, second, and third active regions, wherein the first, second, and third active regions are spaced apart from one another;
• forming first and second n-well regions, wherein the first n-well region includes the first active region, and the second n-well region includes the second active region;
• forming a first p-well region that includes the third active region;
• depositing a semiconductor layer over the field isolation region, the first and second n-well regions, and the first p-well region;
• doping part of the semiconductor layer with a p-type dopant;
• doping a different part of the semiconductor layer with an n-type dopant;
• patterning the semiconductor layer to form a conductive member and a word line;
• forming a p-type doped region within the first n-well region after forming the conductive member;
• forming first, second, and third n-type doped regions after forming the conductive member, wherein:
• the first n-type doped region is within the second n-well region;
• the second n-type doped region is within the first p-well region and is closer to the conductive member than to the word line;
• and
• the third n-type doped region is within the first p-well region and is closer to the word line than to conductive member;
• forming a control gate terminal, an erase terminal, a source terminal, an access terminal, and a drain terminal, wherein:
• the control gate terminal is coupled to the p-type doped region;
• the erase terminal is coupled to the first n-type doped region;
• the source terminal is coupled to the second n-type doped region;
• the access terminal is coupled to the word line, and
• the drain terminal is coupled to the third n-type doped region.