Method for manufacturing a semiconductor device by forming portions thereof at the same time
AssigneeRenesas Electronics Corporation
InventorsRyuta Tsuchiya, Shinichiro Kimura
Life of this patent
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Abstract
A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.
Claims8
A method of manufacturing a semiconductor device, comprising:
- (a) preparing a semiconductor substrate having a first region and a second region, a first silicon oxide layer and a first silicon layer;
- (b) removing the first silicon oxide layer formed over the second region and the first silicon layer formed over the second region, such that the first silicon oxide layer of the first region remains on the semiconductor substrate of the first region and the first silicon layer of the first region remains on the first silicon oxide layer of the first region;
- (c) forming a first well region of a first conductive type in the semiconductor substrate of the first region;
- (d) forming a second well region of the first conductive type in the semiconductor substrate of the second region;
- (e) forming a first gate insulating film over the first silicon layer;
- (f) forming a second gate insulating film over the semiconductor substrate of the second region;
- (g) forming a first gate electrode over the first gate insulating film;
- (h) forming a second gate electrode over the second gate insulating film;
- (i) after the steps (g) and (h), forming first impurity regions of a second conductive type opposite to the first conductive type in the first silicon layer;
- (j) after the steps (g) and (h), forming second impurity regions of the second conductive type in the semiconductor substrate of the second region;
- (k) after the steps (i) and (j), forming first side wall insulating films over side surfaces of the first gate electrode;
- (l) after the steps (i) and (j), forming second side wall insulating films over side surfaces of the second gate electrode;
- (m) after the steps (k) and (l), forming third impurity regions of the second conductive type in the first well region;
- and
- (n) after the steps (k) and (l), forming fourth impurity regions of the second conductive type in the second well region,
- wherein the steps (c) and (d) are performed at the same time,
- wherein the steps (g) and (h) are performed at the same time,
- wherein the steps (i) and (j) are performed at the same time,
- wherein the steps (k) and (l) are performed at the same time, and
- wherein the steps (m) and (n) are performed at the same time.
Dependencies are inferred from the claim text.