Methods and apparatus for processing a received signal using a multiple-step trellis and selection signals for multiple trellis paths

A signal processor for processing a received signal using a multiple-step trellis, comprising:

• an add-compare-select unit for computing three add-compare-select decisions for a given state and for generating a selection signal for each of three paths through a multiple-step trellis into said given state, wherein a first of said three paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of said three paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of said three paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle, wherein each selection signal is based on two of said three add-compare-selection decisions, wherein each of said paths has one or more corresponding survivor bits, and wherein, for each of said paths, one or more of said one or more corresponding survivor bits are selected by said corresponding selection signal;
• and
• a reliability unit that determines a reliability value for at least one bit decision.

A Soft-Output Viterbi algorithm method for processing a signal, comprising the step of:

• determining survivor paths using an add-compare select unit;
• and
• generating a path metric difference D−1 for a first single-step-trellis period of a multiple-step-trellis cycle based on a difference between a first path that is a winning path for each single-step-trellis period of a multiple-step-trellis cycle and another path that is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis of a multiple-step-trellis cycle, wherein said generating step reuses one or more of intermediate path metric values and intermediate path metric difference values computed during said determining step, wherein at least one of said steps of said method is performed by at least one hardware device.

A Soft-Output Viterbi algorithm method for processing a received signal using a multiple-step trellis, comprising the step of:

• defining a plurality of paths through a multiple-step trellis into a given state using at least three selection signals, wherein a first of said plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of said plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of said plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle, wherein one or more of intermediate path metric values and intermediate path metric difference values are reused to generate one or more path metric differences Δ0 and D−1, wherein defining step is performed by at least one hardware device.

A Soft-Output Viterbi algorithm detector or processing a received signal using a multiple-step trellis, comprising:

• a multiple-step-trellis Soft-Output Viterbi algorithm detector that determines values of one or more bits associated with said received signal using a multiple-step trellis and determines one or more reliability values, wherein said determined bits and reliabilities are generated at a rate of the received signal divided by the number of steps in said multiple-step trellis, wherein one or more of intermediate path metric values and intermediate path metric difference values are reused to generate one or more path metric differences Δ0 and D−1.

A Soft-Output Viterbi algorithm method for processing a received signal, comprising:

• determining values of one or more bits associated with said received signal using a multiple step trellis;
• and
• determining one or more reliability values, wherein said determined bits and said reliabilities are generated at a rate of the received signal divided by the number of steps in said multiple-step trellis, wherein one or more of intermediate path metric values and intermediate path metric difference values are reused to generate one or more path metric differences Δ0 and D−1 wherein at least one of said steps of said method is performed by at least one hardware device.