Back to results
US 8,405,225 B2Granted
Three-dimensional integrated circuits with protection layers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.
Claims20
A device comprising:
- a supporter wafer free from active devices therein, wherein the supporter wafer comprises:
- a substrate;
- and
- a first bonding pad over the substrate;
- a first die over the supporter wafer, wherein the first die comprises:
- a first surface;
- a second surface opposite the first surface;
- and
- a second bonding pad at the first surface and bonded to the first bonding pad of the supporter wafer through flip-chip bonding;
- a protection layer having a vertical portion on a sidewall of the first die;
- and
- a coating formed laterally adjacent to the vertical portion of the protection layer.
9 more elements
A device comprising:
- a supporter wafer comprising:
- a dielectric substrate;
- and
- a plurality of bonding pads over the dielectric substrate;
- a first die comprising:
- a first surface;
- a second surface opposite the first surface;
- a first bonding pad at the first surface and bonded to one of the plurality of bonding pads of the supporter wafer;
- and
- a first conductive through-via penetrating from the second surface to the first surface of the first die, wherein the first conductive through-via is electrically coupled to the first bonding pad;
- a protection layer having a vertical portion on a sidewall of the first die, and a horizontal portion extending over the supporter wafer;
- and
- a coating overlapping the horizontal portion of the protection layer and substantially level with the vertical portion of the protection layer.
10 more elements
A device comprising:
- a supporter wafer free from active devices therein, wherein the wafer comprises a first die and a second die, each comprising:
- a substrate;
- and
- a first bonding pad over the substrate;
- a third and a fourth die over the wafer and neighboring each other, with no other dies there between, wherein each of the third and the fourth dies comprises:
- a first surface;
- a second surface opposite the first surface;
- and
- a second bonding pad at the first surface and bonded to the first bonding pad of the first die and the second die, respectively;
- and
- a protection layer comprising a first portion encircling the third die, and a second portion encircling the fourth die, wherein the first portion and the second portion are spaced apart from each other.
8 more elements
Dependencies are inferred from the claim text.