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US 8,397,031 B2Granted
Apparatus, processor and method of cache coherency control
AssigneeNEC Computertechno, Ltd.
InventorYoshiaki Watanabe
Life of this patent
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Abstract
An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory.
Claims28
A cache coherency control circuit that shares a bus with a plurality of processors,
- wherein each of the processors includes a cache memory,
- wherein the cache coherency control circuit is exterior to each of said processors, and suspends a request of at least one of the processors during a predetermined period when one processor of said plurality of processors fetches data from a main memory to the cache memory of said one processor of the plurality of processors,
- wherein the cache coherency control circuit suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory,
- wherein said cache coherency control circuit comprises:
- a read administration unit;
- a cache line address information store unit operatively coupled to the read administration unit;
- and
- a pending instruction unit, operatively coupled to the cache line address information unit that outputs spending instruction that includes a cache line address stored in the cache line address information store unit, and
- wherein, when the read administration unit receives a read request from one of the processors, the read administration unit performs a read operation on a condition that a cache line address corresponding to the read request is not stored in the cache line address information store unit.
6 more elements
A processor, comprising:
- a cache memory;
- a request issuing circuit which issues a request when a cache miss occurs;
- and
- a controller which suspends issuing of the request during a predetermined period upon receiving a suspension signal from an external controller that fetches data to the cache memory according to the cache miss,
- wherein said external controller comprises:
- a read administration unit;
- a cache line address information store unit operatively the read administration unit;
- and
- a pending instruction unit, operatively coupled to the cache line address information store unit, that outputs a pending instruction that includes a cache line address stored in the cache line address information store unit, and
- wherein, when the read administration unit receives a read request from the processor, the read administration unit performs a read operation on a condition that a cache line address corresponding to the read request is not stored in the cache line address information store unit.
7 more elements
A method of controlling a plurality of processors each of which includes a cache memory, by a controller which is exterior to said each of the processors, said method comprising:
- fetching, by one processor of said plurality of processors, data from a main memory to the cache memory of said one processor of the plurality of processors according to a cache miss;
- and
- suspending a request of the processors, except said one processor that fetches the data from the main memory to the cache memory of said one processor of the plurality of processors, during a predetermined period,
- wherein said controller comprises:
- a read administration unit;
- a cache line address information store unit operatively coupled to the read administration unit;
- and
- a pending instruction unit, operatively coupled to the cache line address information store unit, that outputs a pending instruction that includes a cache line address stored in the cache line address information store unit, and
- wherein when the read administration unit receives a read request from said one processor of the plurality of processors, the read administration unit performs a read operation on a condition that a cache line address corresponding to the read request is not stored in the cache line address information store unit.
6 more elements
Dependencies are inferred from the claim text.