Digital pulse width modulator
AssigneePowervation Limited
InventorsEamon O'Malley, Karl Rinne
Life of this patent
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Abstract
A DPWM (1) has a locked loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each cell in the loop (35). A multiplexer (5) selects one of the cell outputs at any one time. This allows the DPWM (1) to have a greater resolution which would otherwise be achieved with the same input clock. The resolution is further increased using an interpolator. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.
Claims22
A switched mode power converter controller (SMPCC) for providing a PWM control signal to a power switch in a switching cycle, the SMPCC controller having a hybrid Digital Pulse Width Modulator (DPWM), the hybrid DPWM effecting the PWM control signal at a switching point at a resolution of N bits across the switching cycle, the hybrid DPWM comprising:
- a) a counter circuit responsive to a clock signal and determining the switching point at a first resolution, the counter circuit providing an enable output signal at the determined switching point,
- b) a locked loop for delaying the clock signal to provide multiple clock phases from the clock signal,
- c) a first multiplexer for selecting a first one of the multiple clock phases and a second one of the multiple clock phases adjacent to the selected first clock phase in response to a received first select signal,
- d) an interpolator responsive to the selected first and second clock phases and interpolating between the selected two clock phases to provide a plurality of interpolated phases between the selected two clock phases,
- e) a second multiplexer for selecting one of the plurality of interpolator phases in response to a received second select signal for use as the PWM control signal.
A switched mode power converter controller (SMPCC) for providing a plurality of control signals for operating individual power switches within a switching cycle of a switching converter,
- the SMPC controller having a hybrid Digital Pulse Width Modulator (DPWM), the hybrid DPWM generating each of the control signals at switching points across the switching cycle at a resolution of N bits, the hybrid DPWM comprising:
- a) a counter circuit responsive to a clock signal,
- b) a plurality of controllers comprising a plurality of comparators, each of the comparators being associated with an individual control signal and determining the switching point of the control signal at a resolution less than N and providing individual enabled signals at said determined switching points,
- c) a locked loop for delaying the clock signal to provide a plurality of clock phases from the clock signal,
- d) a first set of multiplexors, each multiplexor for selecting two of the clock phases from the locked loop in response to a select signal,
- e) a set of interpolators each interpolator interpolating between the selected two phases from a multiplexor of the first set of multiplexors to provide a plurality of interpolated outputs,
- f) a second set of multiplexers, each of the multiplexors of the second set for selecting an interpolated output from an interpolator.
Dependencies are inferred from the claim text.