Ensuring minimum gate speed during startup of gate speed regulator

A computing device comprising:

• digital circuitry;
• and
• a gate speed regulator operable to generate a supply voltage applied to the digital circuitry, the gate speed regulator comprising:
• a frequency synthesizer operable to generate a first reference frequency;
• a propagation delay oscillator operable to generate a first oscillation frequency in response to the supply voltage, wherein the first oscillation frequency is compared to the first reference frequency to generate a first error signal;
• a reference oscillator operable to generate a second reference frequency in response to a reference voltage;
• a startup oscillator operable to generate a second oscillation frequency in response to the supply voltage, wherein the second oscillation frequency is compared to the second reference frequency to generate a second error signal;
• and
• an adjustable circuit, responsive to the first and second error signals, for adjusting the supply voltage applied to the digital circuitry.