Time base generator and method for providing a first clock signal and a second clock signal
AssigneeSiemens Aktiengesellschaft
InventorGeorge Burcea
Life of this patent
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Abstract
A time base generator and method for providing a first clock signal and a second clock signal comprising generating the first clock signal at a first clock frequency, dividing the first clock frequency by a first integer to produce a first auxiliary signal, dividing the second clock signal by a second integer to produce a second auxiliary signal, generating an error signal by individually weighting and comparing cycle durations or phasing of the first and second auxiliary signals, and generating the second clock signal by a voltage-controlled oscillator controlled by the error signal such that two clock signals of slightly different frequencies with defined time or phase delay are provided.
Claims8
A time base generator for providing a first clock signal and a second clock signal, the frequencies of said clock signals being different, said time base generator comprising:
- a clock signal generator providing the first clock signal at the first clock frequency;
- a first frequency divider configured to divide the first clock frequency by a first integer to produce a first auxiliary signal;
- a second frequency divider configured to divide the second clock signal by a second integer to produce a second auxiliary signal;
- a phase/period comparator comprising a first time to voltage converter receiving the first auxiliary signal, a second time-to-voltage converter receiving the second auxiliary signal and a voltage comparator connected to the first and a second time to voltage converter, the phase/period comparator being configured to generate an error signal by individually weighting and comparing the cycle durations or phasing of the first and second auxiliary signals;
- and
- a voltage-controlled oscillator controlled by the error signal to generate the second clock signal.
A method for providing a first clock signal and a second clock signal, frequencies of the clock signals being different from each other, said method comprising:
- providing the first clock signal at a first clock frequency;
- dividing the first clock frequency by a first integer to produce a first auxiliary signal;
- dividing a second clock signal by a second integer to produce a second auxiliary signal;
- generating an error signal by individually weighting and comparing cycle durations or phasing of the first and second auxiliary signals, time-to-voltage converting the first and second auxiliary signals and comparing voltages obtained from the time-to-voltage converted first and second auxiliary signals voltages;
- and
- generating, by a voltage-controlled oscillator, the second clock signal, the voltage controlled oscillator being controlled by the error signal.
Dependencies are inferred from the claim text.