Low power, high performance, heterogeneous, scalable processor architecture
AssigneeiCelero LLC
InventorsAmit Ramchandran, John Reid Hauser, Jr.
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Abstract
One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
Claims18
A heterogeneous, scalable processor, said processor comprising:
- a first heterogeneous programmable integrated circuit sub-processor configured for 16, 24, 32 and 64-bit processing;
- and
- a second heterogeneous programmable integrated circuit sub-processor configured for 8, 4 and 1-bit processing,
- wherein at least one of the first and second sub-processors include one or more functional units each including a memory and configured for rearrangement of data values to and from the memory, and
- wherein each of the first and second sub-processors can only execute one function at a time with an internal control block configured to synchronize an order of function execution.
A method for operating a heterogeneous, scalable processor, said method comprising:
- performing 16, 24, 32 and 64-bit processing with a first heterogeneous programmable integrated circuit sub-processor;
- performing 8, 4 and 1-bit processing with a second heterogeneous programmable integrated circuit sub-processor;
- rearranging data values to and from a memory included in one or more functional units provided in at least one of the first and second sub-processors;
- and
- executing only one function at a time with an internal control block included in each of the first and second sub-processors and configured to synchronize an order of function execution.
A computer program product for operating a heterogeneous, scalable processor, and including one or more computer readable instructions embedded on a tangible, non-transitory computer readable medium and configured to cause one or more computer processors to perform the steps of:
- performing 16, 24, 32 and 64-bit processing with a first heterogeneous programmable integrated circuit sub-processor;
- performing 8, 4 and 1-bit processing with a second heterogeneous programmable integrated circuit sub-processor;
- rearranging data values to and from a memory included in one or more functional units provided in at least one of the first and second sub-processors;
- and
- executing only one function at a time with an internal control block included in each of the first and second sub-processors and configured to synchronize an order of function execution.
Dependencies are inferred from the claim text.