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AssigneeThe Regents of the University of California
InventorsChenming Hu, Anupama Bowonder, Pratik Patel, Daniel Chou, Prashant Majhi
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Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.
A tunneling transistor comprising:
A tunneling transistor comprising:
A tunneling transistor comprising:
Dependencies are inferred from the claim text.