Gate-all-around nanowire field effect transistors
AssigneeInternational Business Machines Corporation
InventorsSarunya Bangsaruntip, Josephine B. Chang, Guy M. Cohen, Jeffrey W. Sleight
Life of this patent
Estimating the term…
Abstract
A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
Claims35
A method for forming a nanowire field effect transistor (FET) device, the method comprising:
- forming a suspended nanowire over a semiconductor substrate;
- forming a first gate structure around a first portion of the nanowire;
- forming a first protective spacer adjacent to sidewalls of the first gate structure and around portions of the nanowire extending from the first gate structure;
- removing exposed portions of the nanowire left unprotected by the first spacer;
- and
- epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.
A method for a nanowire field effect transistor (FET) device, the method comprising:
- forming a suspended nanowire over a semiconductor substrate;
- forming a gate structure around a portion of the nanowire;
- forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure;
- removing exposed portions of the nanowire to form a cavity defined by the nanowire surrounded by the gate structure and the spacer;
- and
- epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire.
A nanowire field effect transistor (FET) device, comprising:
- a channel region including a silicon portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate structure disposed circumferentially around the silicon portion;
- a source region including a first doped epi-silicon nanowire extension contacting the first distal end of the silicon portion;
- and
- a drain region including a second doped epi-silicon nanowire extension contacting the second distal end of the silicon portion.
A nanowire field effect transistor (FET) device, comprising:
- a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion;
- a first cavity defined by the first distal end of the silicon portion and an inner diameter of the gate structure;
- a second cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure;
- a source region including a first doped epi-silicon nanowire extension epitaxially extending from the first distal end of the silicon portion in the first cavity;
- and
- a drain region including a second doped epi-silicon nanowire extension epitaxially extending from the second distal end of the silicon portion in the second cavity.
Dependencies are inferred from the claim text.