Structure for a frequency adaptive level shifter circuit

A phase-lock loop device that generates a frequency adaptive clock signal across voltage domain boundaries comprising:

• a voltage controlled oscillator that receives an analog reference voltage;
• and
• a level shifter that receives an analog signal from the voltage controlled oscillator and the analog reference voltage input to the voltage controlled oscillator and outputs the frequency adaptive clock signal, the level shifter further comprising:
• a capacitor electrically connected to the output of the voltage controlled oscillator;
• a resistor coupled to the output of the capacitor;
• a transistor coupled to the output of the resistor that has a gate connected to the analog reference voltage that enables the level shifter to be frequency adaptive by making the transistor resistance very high at low voltage on the transistor and making the transistor resistance very low at high voltage on the transistor.