Multi-chip package and method of manufacturing thereof

A multi-chip package comprising:

• a substrate having first and second bonding pads on a top surface thereof;
• a first chip connected to the first bonding pads on the substrate;
• a support layer formed on the substrate so as to surround one or more lateral surfaces of the first chip;
• a set of openings formed in the support layer so as to expose the second bonding pads;
• and
• a second chip formed on the support layer and the first chip, the second chip having a portion that overhangs the first chip and is connected to the second bonding pads using wires that pass through respective ones of the openings.

A method of manufacturing a multi-chip package, the method comprising:

• forming a substrate having first and second bonding pads on a top surface thereof;
• mounting a first chip on the substrate and connecting chip pads on the first chip to the first bonding pads on the substrate;
• forming an insulating layer on the substrate so as to surround lateral surfaces of the first chip;
• forming a set of openings in the insulating layer so as to expose the second bonding pads;
• mounting a second chip on the insulating layer and the first chip, the second chip having at least a portion that overhangs the first chip;
• and
• connecting chip pads on the second chip to the second bonding pads using wires that pass through respective ones of the openings.