Wafer level chip scale package

A semiconductor device comprising:

• a semiconductor substrate having first and second surfaces and a sidewall between the first and second surfaces;
• a first conductive pad on the first surface of the device in electrical contact with a first semiconductor device structure within the substrate;
• a second conductive pad on the second surface of the device in electrical contact with a second semiconductor device structure within the substrate;
• a notch on the sidewall running from the first surface to the second surface, wherein said notch does not extend across the entire length of a die;
• an insulator layer on the first surface and on the sidewall in the notch;
• an electrically conductive layer on part of the insulator layer on the sidewall, wherein the conductive layer is in electrical contact with the second conductive pad, allowing access to the second conductive pad from the first surface, wherein the insulator layer prevents the conductive layer from making contact between the second conductive pad and the sidewall of the semiconductor substrate, wherein the device is a vertical field effect transistor, and wherein the first semiconductor device structure comprises a source region and wherein the second semiconductor device structure comprises a drain region.

A circuit package assembly, comprising:

• a first vertical metal oxide semiconductor field effect transistor (MOSFET) having top source and gate and a bottom drain, wherein the first vertical MOSFET includes at least two of source, gate and drain electrodes which are accessible on both front and back sides of the first MOSFET;
• and
• a second vertical metal oxide semiconductor field effect transistor (MOSFET) having top source and gate and a bottom drain, wherein the second vertical MOSFET includes at least two of source, gate and drain electrodes are accessible on both front and back sides of the second MOSFET,
• wherein the first and second MOSFETs are stacked together.

A wafer level method for manufacturing a plurality of semiconductor devices, comprising:

• a) forming a plurality of semiconductor device dies separated by designated scribe lines on a semiconductor wafer comprising a semiconductor substrate, wherein each device die includes a first conductive pad on a first surface and a second conductive pad on a second surface, wherein the second surface is on the opposite side of the substrate as the first surface and separated by a sidewall, wherein the first conductive pad is in electrical contact with a first semiconductor device structure in the substrate and the second conductive pad is in electrical contact with a second semiconductor device structure in the substrate on a second surface;
• b) forming one or more through holes through the substrate at the scribe lines between adjacent dies, wherein said through holes do not extend across the entire length of a semiconductor die;
• c) forming an insulating layer on a sidewall of one or more of the through holes;
• d) forming a conductive layer over the insulating layer on the first surface and on the sidewall, wherein the conductive layer is in electrical contact with the second conductive pad allowing access to the second conductive pad from the first surface, wherein the insulator layer prevents the conductive layer from making contact between the second conductive pad and the sidewall of the semiconductor substrate;
• c′) forming a second insulating layer on a portion of a sidewall of a different one or more of the through holes;
• and
• d′) forming a second conductive layer over the second insulating layer on the second surface and on the sidewall of the different one or more through holes, wherein the second conductive layer is in electrical contact with the first conductive pad allowing access to the first conductive pad from the second surface, wherein the second insulator layer prevents the second conductive layer from making contact between the first conductive pad and the sidewall of the semiconductor substrate.