Low offset input circuit and transmission system with the input circuit

A low offset input circuit mounted on a receiver circuit of a high-speed transmission system that includes a transmitter circuit, the receiver circuit, and a transmission line that transmits a transmission signal from the transmitter circuit to the receiver circuit, the low offset input circuit comprising:

• a differential input circuit that receives a differential transmission signal from the transmission line and amplifies the differential transmission signal to generate a first differential output signal;
• an adder-subtractor circuit unit that generates a second differential output signal at an output node by performing addition or subtraction of a first offset voltage to the first differential output signal, the adder-subtractor circuit unit including an adjusting voltage generating circuit unit that generates the first offset voltage to correspond to a value of a digital setting signal at a predetermined resolution received by the adder-subtractor circuit;
• a first switch which short-circuits differential input nodes of the differential input circuit to each other when operated in an ON state;
• a second switch having a first end and a second end, the first end being coupled with the output node of the adder-subtractor circuit;
• a detecting circuit unit for detecting an offset voltage of the differential input circuit using the second differential output signal when the first switch and the second switch are operated in an ON state, the detecting circuit unit including an amplifier unit that amplifies the second differential output signal to perform offset reduction of the amplifier unit and a comparator circuit that performs a binary determination of the second differential output signal amplified by the amplifier unit to determine a polarity of the second differential output signal, and outputs a result of the binary determination;
• and
• an adjusting and holding circuit unit that monitors the result of the binary determination output by the comparator circuit to set the value of the digital setting signal to indicate the detected offset voltage of the input circuit, holds the detected offset voltage as the value of the digital setting signal when the polarity of the second differential output signal has been reversed, and performs feedback of the digital setting signal to the adder-subtractor circuit unit,
• wherein the amplifier unit includes:
• a third switch having a first end coupled to the second end of the second switch, a first differential amplifier, a fourth switch having a first end connected to an output node of the first differential amplifier and a second end connected to a capacitor that accumulates an offset voltage of the first differential amplifier during an auto-zeroing operation time period in which the third and fourth switches are switched to first states, and an adder-subtractor that subtracts the offset voltage accumulated in the capacitor from the second differential output signal that is input from the third switch to the first differential amplifier to cancel an offset voltage of the first differential amplifier during a normal operation time period in which the third and fourth switches are switched to second states.

A signal transmission system comprising a transmitter circuit, a receiver circuit, and a transmission line transmitting a transmission signal from the transmitter circuit to the receiver circuit,

• wherein the receiver circuit includes:
• an input circuit that receives differential transmission signals from the transmission line at an input node and amplifies the transmission signals to generate first differential output signals;
• wherein the transmitter circuit includes:
• a first switch coupled to the input node of the input circuit and configured to output only an offset component of the transmitter circuit to the receiver circuit when operated in an ON state;
• and
• wherein the receiver circuit further includes:
• an adder-subtractor circuit unit that generates second differential output signals at an output node by performing addition or subtraction of a first offset voltage to the first differential output signals, the adder-subtractor circuit unit including an adjusting voltage generating circuit unit that generates the first offset voltage to correspond to a value of a digital setting signal at a predetermined resolution received by the adder-subtractor circuit;
• a second switch having a first end and a second end, the first end being coupled with the output node of the adder-subtractor circuit;
• a detecting circuit unit for detecting an offset voltage of the input circuit using the second differential output signals when the first switch and the second switch are operated in an ON state, the detecting circuit unit including an amplifier unit that amplifies the second differential output signals to perform offset reduction of the amplifier unit and a comparator circuit that performs a binary determination of the second differential output signal amplified by the amplifier unit and outputs a result of the binary determination;
• and
• an adjusting and holding circuit unit that monitors the result of the binary determination output by the comparator circuit to set the value of the digital setting signal to indicate the detected offset voltage of the input circuit holds the detected offset voltage as the value of the digital setting signal when the binary determination result transits, and performs feedback of the digital setting signal to the adder-subtractor circuit unit, and
• wherein the amplifier unit includes a third switch having a first end coupled to the second end of the second switch, a first amplifier, a fourth switch having a first end connected to an output node of the first amplifier and a second end connected to a capacitor that accumulates an offset voltage of the first amplifier during an auto-zeroing operation time period in which the third and fourth switches are switched to first states, and an adder-subtractor that subtracts the offset voltage accumulated in the capacitor from the second differential output signals that are input from the third switch to the first amplifier to cancel an offset voltage of the first amplifier during a normal operation time period in which the third and fourth switches are switched to second states.