Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings

A method for creating a layout of an integrated circuit, comprising:

• defining, using a computer a layout of a dynamic array section including a gate electrode level region that forms part of a gate electrode level of the integrated circuit device, the gate electrode level region having linear conductive features defined in accordance with a gate level virtual grate, wherein the gate level virtual grate is defined by a framework of parallel virtual lines extending in a first direction and spaced at about a constant pitch,
• wherein each of at least three virtual lines of the gate level virtual grate has at least one linear conductive feature defined thereon, wherein the at least three virtual lines of the gate level virtual grate are consecutively positioned in a side-by-side manner, and
• wherein a first virtual line of the at least three virtual lines of the gate level virtual grate has a first linear conductive segment and a second linear conductive segment defined thereon and separated by a first end-to-end spacing, each of the first and second linear conductive segments having inner and outer ends, wherein the inner ends of the first and second linear conductive segments are located next to the first end-to-end spacing, and
• wherein a second virtual line of the at least three virtual lines of the gate level virtual grate has a third linear conductive segment and a fourth linear conductive segment defined thereon and separated by a second end-to-end spacing, each of the third and fourth linear conductive segments having inner and outer ends, wherein the inner ends of the third and fourth linear conductive segments are located next to the second end-to-end spacing, and
• wherein a third virtual line of the at least three virtual lines of the gate level virtual grate has a fifth linear conductive segment defined thereon, the fifth linear conductive segment having a first end substantially aligned in the first direction with the outer ends of the first and third linear conductive segments, and the fifth linear conductive segment having a second end substantially aligned in the first direction with the outer ends of the second and fourth linear conductive segments, and
• wherein a size of the first end-to-end spacing as measured in the first direction is substantially equal to a size of the second end-to-end spacing as measured in the first direction.

A data storage device having computer executable program instructions stored thereon for creating a layout of an integrated circuit, comprising:

• program instructions for defining a layout of a dynamic array section including a gate electrode level region that forms part of a gate electrode level of the integrated circuit device, the gate electrode level region having linear conductive features defined in accordance with a gate level virtual grate, wherein the gate level virtual grate is defined by a framework of parallel virtual lines extending in a first direction and spaced at about a constant pitch,
• wherein each of at least three virtual lines of the gate level virtual grate has at least one linear conductive feature defined thereon, wherein the at least three virtual lines of the gate level virtual grate are consecutively positioned in a side-by-side manner, and wherein a first virtual line of the at least three virtual lines of the gate level virtual grate has a first linear conductive segment and a second linear conductive segment defined thereon and separated by a first end-to-end spacing, each of the first and second linear conductive segments having inner and outer ends, wherein the inner ends of the first and second linear conductive segments are located next to the first end-to-end spacing, and
• wherein a second virtual line of the at least three virtual lines of the gate level virtual grate has a third linear conductive segment and a fourth linear conductive segment defined thereon and separated by a second end-to-end spacing, each of the third and fourth linear conductive segments having inner and outer ends, wherein the inner ends of the third and fourth linear conductive segments are located next to the second end-to-end spacing, and
• wherein a third virtual line of the at least three virtual lines of the gate level virtual grate has a fifth linear conductive segment defined thereon, the fifth linear conductive segment having a first end substantially aligned in the first direction with the outer ends of the first and third linear conductive segments, and the fifth linear conductive segment having a second end substantially aligned in the first direction with the outer ends of the second and fourth linear conductive segments, and
• wherein a size of the first end-to-end spacing as measured in the first direction is substantially equal to a size of the second end-to-end spacing as measured in the first direction.