Nonvolatile memory device and system, and method of programming a nonvolatile memory device

A memory system comprising:

• a nonvolatile memory comprising a control logic, an address decoder, and a memory cell array, the memory cell array comprising rows and columns of N-bit multi-level cell (MLC) memory cells, wherein each row of MLC memory cells is configured to stored N pages of data;
• a memory controller including a host interface for interfacing with an external device, a memory interface for interfacing with the nonvolatile memory, a central processing unit, a buffer memory, and an error correction code (ECC) circuit,
• the memory controller configured to execute a partial interleave process in which the N pages of data are divided into M page groups, where M is a positive number and where each page group includes at least one of the N pages of data, and in which each of the M page groups is applied to the ECC circuit to generate parity bits for the respective M page groups, wherein a bit-error rate (BER) among the pages within each of the M groups is equalized by the partial interleave process.