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US 8,354,868 B2Granted
Clock circuit for a microprocessor
AssigneeResearch In Motion Limited
InventorsMark A. J. Carragher, John William Wynen
Life of this patent
Estimating the term…
Abstract
A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.
Claims16
A mobile communication device comprising:
- a microprocessor;
- an analog clock circuit configured to generate an oscillating output on an output line to synchronize the microprocessor;
- and
- a digital clock circuit configured to generate a digital clock output, on said output line, having a frequency that is substantially equal to the frequency of the oscillating output;
- wherein only one of the oscillating output and the digital clock output is enabled as a clock signal at a time.
2 more elements
A mobile communication device comprising:
- a first clock circuit configured to generate a first clock output;
- and
- a second clock circuit configured to generate a second clock output having a frequency that is substantially equal to the frequency of the first clock output;
- and
- a controller configured to selectively enable only one of the clock outputs at a time to be enabled as a clock signal, and to switch from one of the first clock output being enabled as the clock signal to the second clock output being enabled as the clock signal in a manner that is synchronized with the first clock output.
2 more elements
A mobile communication device comprising:
- a first clock circuit configured to generate a first clock output;
- and
- a second clock circuit configured to generate a second clock output having a frequency that is substantially equal to the frequency of the first clock output;
- and
- a controller configured to switch from the first clock output being enabled as a clock signal to the second clock output being enabled as the clock signal, and to wait for an edge of the first clock output, indicating the beginning of a new cycle of the first clock output, before switching from the first clock output to the second clock output.
2 more elements
Dependencies are inferred from the claim text.