# US 8,352,651 B2 · Devices, systems, and methods regarding programmable logic controller communications

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- Number: US 8,352,651 B2
- Document ID: US8352651B2
- Status: Granted
- Kind: B2
- Application number: 12/137,117
- Filed: 2008-06-11
- Published: 2008-12-18
- Granted: 2013-01-08
- Earliest claimed: 2007-06-12
- Assignees: Siemens Aktiengesellschaft
- Inventors: Steven Perry Parfitt
- Web page: https://patentgrep.com/patent/US8352651B2

## CPC

- G05B 19/054: {Input/output}
- G05B 2219/15133: Opto isolation, optical separation
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)

## Abstract

Certain exemplary embodiments can provide a system, which can comprise a signal interface that is adapted to transmit a signal between a programmable logic controller and an Input/Output (I/O) module. The programmable logic controller can be communicatively coupled to the I/O module via an opto-coupler, which can be adapted to electrically isolate the programmable logic controller from the I/O module.

## Claims

### Claim 1

A system comprising:
a signal interface circuit including circuitry for integrating a control sub-signal within a clock sub-signal, wherein the signal interface circuit:
forms an integrated signal comprising the clock sub-signal and the control sub-signal; and
transmits the integrated signal between a programmable logic controller and an Input/Output (I/O) module, said programmable logic controller communicatively coupled to said I/O module via a single opto-coupler,
wherein said clock sub-signal provides temporal information regarding said integrated signal,
wherein said control sub-signal comprises a framing signal indicative of a completion of a register transfer, and
a circuit recovers said clock sub-signal and said control sub-signal from said integrated signal, wherein the control sub-signal is recovered via said circuit detecting said control sub-signal by differentiating short length pulses from pulses that have a longer length.

### Claim 2 (depends on 1)

The system of claim 1, further comprising:
said I/O module.

### Claim 3 (depends on 1)

The system of claim 1, further comprising:
said opto-coupler.

### Claim 4 (depends on 1)

The system of claim 1, further comprising:
said programmable logic controller.

### Claim 5 (depends on 1)

The system of claim 1, wherein:
said signal interface circuit recovers an incoming clock sub-signal from an incoming signal that comprises said incoming clock sub-signal integrated with an incoming control sub-signal.

### Claim 6 (depends on 1)

The system of claim 1, wherein:
said signal interface circuit comprises a counter that provides said clock sub-signal to combinatorial logic, and
said combinatorial logic integrates said clock sub-signal and said control sub-signal to form said integrated signal.

### Claim 7 (depends on 1)

The system of claim 1, wherein:
said signal interface circuit comprises a counter that provides said clock sub-signal to combinatorial logic, and
said combinatorial logic integrates said clock sub-signal, said control sub-signal, and a data sub-signal to form said integrated signal.

### Claim 8 (depends on 1)

The system of claim 1, wherein:
said signal interface circuit comprises a counter that provides said clock sub-signal to combinatorial logic,
said combinatorial logic integrates said clock sub-signal and said control sub-signal to form said integrated signal, and
said combinatorial logic provides an initiation signal that resets said counter at an end of said integrated signal.

### Claim 9 (depends on 1)

The system of claim 1, wherein:
said signal interface circuit comprises a pulse high detector.

### Claim 10 (depends on 1)

The system of claim 1, wherein:
said signal interface circuit comprises a pulse high detector that recovers said control sub-signal from said integrated signal.

### Claim 11 (depends on 1)

The system of claim 1, wherein:
said signal interface circuit comprises a pulse low detector that recovers said control sub-signal from said integrated signal.

### Claim 12 (depends on 1)

The system of claim 1, wherein:
said integrated signal comprises a data sub-signal, said data sub-signal comprising information from said register transfer.

### Claim 13

A method comprising:
integrating a control sub-signal within a clock sub-signal using a signal interface circuit including circuitry forming an integrated signal, the integrated signal including the clock sub-signal and the control sub-signal; and
causing the integrated signal to be transmitted between a programmable logic controller and an Input/Output (I/O) module via the signal interface circuit, said programmable logic controller using said integrated signal to control a process, said programmable logic controller communicatively coupled to said I/O module via an opto-coupler,
wherein:
said clock sub-signal provides temporal information regarding said integrated signal,
said control sub-signal comprises a framing signal indicative of a completion of a register transfer, and
a circuit receiving said integrated signal recovers said clock sub-signal and said control sub-signal from said integrated signal, wherein the control sub-signal is recovered via said circuit detecting said control sub-signal by differentiating short length pulses from pulses that have a longer length.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
recovering said control sub-signal from said integrated signal.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
via a pulse high detector, recovering said control sub-signal from said integrated signal.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
via a pulse low detector, recovering said control sub-signal from said integrated signal.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
transmitting said integrated signal.

### Claim 18 (depends on 13)

The method of claim 13, further comprising:
integrating said control sub-signal into said integrated signal.

### Claim 19 (depends on 13)

The method of claim 13, further comprising:
via a combinatorial logic circuit, integrating said control sub-signal into said integrated signal.

### Claim 20 (depends on 13)

The method of claim 13, further comprising:
automatically resetting a counter of said signal interface circuit responsive to an end of said integrated signal.

### Claim 21

A non-transitory machine-readable medium comprising machine-implementable instructions for activities comprising:
integrating a control sub-signal within a clock sub-signal using a signal interface circuit including circuitry forming an integrated signal, the integrated signal comprising a clock sub-signal and a control sub-signal; and
causing the integrated signal to be transmitted between a programmable logic controller and an Input/Output (I/O) module via the signal interface circuit, said programmable logic controller using said integrated signal to control a process, said programmable logic controller communicatively coupled to said I/O module via an opto-coupler,
wherein:
said clock sub-signal provides temporal information regarding said integrated signal,
said control sub-signal comprises a framing signal indicative of a completion of a register transfer, and
a circuit receiving said integrated signal recovers said clock sub-signal and said control sub-signal from said integrated signal, wherein the control sub-signal is recovered via said circuit detecting said control sub-signal by differentiating short length pulses from pulses that have a longer length.