Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method

A sigma-delta modulator, comprising:

• a processing circuit, arranged to perform a subtraction for an input signal and a first analog information to generate a subtraction signal, and perform an integration for the subtraction signal and a second analog information to generate an integrated signal;
• a quantizer, arranged to perform a successive approximation register (SAR) analog-to-digital conversion for the integrated signal to generate a digital information;
• a truncater, arranged to perform a truncation to generate a truncated information according to the digital information;
• and
• a feedback circuit, coupled between the processing circuit and the truncater, arranged to perform a digital-to-analog conversion for the truncated information to generate the first analog information and the second analog information;
• wherein an order of the truncation is lower than an order of the integration.

A sigma-delta modulation method, comprising:

• receiving an input signal and an analog information, and performing an integration process to generate an integrated signal by performing an integration upon a difference between the input signal and the analog information;
• performing a successive approximation register (SAR) analog-to-digital conversion to generate a digital information according to the integrated signal;
• performing a truncation to generate a truncated information according to the digital information;
• and
• performing a feedback process to generate the analog information according to the truncated information;
• wherein an order of the truncation is lower than an order of the integration.

A sigma-delta modulation method, comprising:

• performing a subtraction for an input signal and a first analog information to generate a subtraction signal, and performing an integration for the subtraction signal and a second analog information to generate an integrated signal;
• performing a successive approximation register (SAR) analog-to-digital conversion for the integrated signal to generate a digital information;
• performing a truncation to generate a truncated information according to the digital information;
• and
• performing a digital-to-analog conversion for the truncated information to generate the first analog information and the second analog information;
• wherein an order of the truncation is lower than an order of the integration process.