Supplementary timing recovery
AssigneeMarvell International Ltd.
InventorsJin Xie, Mats Oberg
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes an analog to digital converter (ADC) configured to receive an analog input signal, sample the analog input signal based on a sampling clock signal, and convert the sampled analog input signal into a digital output signal, an equalizer configured to equalize the digital output signal, a phase-shift module configured to phase-shift the equalized digital output signal based on a phase-shift signal, and a timing compensation module coupled to the phase-shift module to detect a timing error, and to adjust the phase-shift signal based on the timing error.
Claims20
A signal processing circuit, comprising:
- a first timing compensation module configured to detect a first timing error based on a digital output signal converted from sampled analog input signal based on a sampling clock signal, and to adjust the sampling clock signal based on the first timing error;
- an equalizer configured to equalize the digital output signal;
- and
- a second timing compensation module configured to detect a second timing error based on the equalized digital output signal, and to adjust a phase-shift signal based on the second timing error.
A method for signal processing, comprising:
- detecting a first timing error based on a digital output signal converted from sampled analog input signal based on a sampling clock signal;
- adjusting the sampling clock signal based on the first timing error;
- equalizing the digital output signal;
- detecting a second timing error based on the equalized digital output signal;
- and
- adjusting a phase-shift signal based on the second timing error.
An apparatus for reading a non-transitory optical medium, comprising:
- an optical pick-up unit configured to generate a data signal corresponding to data stored on the non-transitory optical medium;
- an analog signal processing path to generate an analog input signal based on the data signal;
- a first timing compensation module configured to detect a first timing error based on a digital output signal converted from sampled analog input signal based on a sampling clock signal, and to adjust the sampling clock signal based on the first timing error;
- an equalizer configured to equalize the digital output signal;
- a second timing compensation module configured to detect a second timing error based on the equalized digital output signal, and to adjust a phase-shift signal based on the second timing error.
Dependencies are inferred from the claim text.