Semiconductor memory device

A semiconductor memory device comprising:

• a bitline sensing amp configured to detect and amplify data of a pair of bitlines, the data of the pair of bitlines being memory cell data transmitted to the pair of bitlines;
• a column selecting unit configured to transmit the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal;
• a dataline precharging unit configured to precharge the pair of local datalines to a precharging voltage level in response to a precharging signal;
• and
• a dataline sensing amp configured to detect and amplify data of the pair of local datalines,
• wherein the dataline sensing amp comprises:
• a sensing control unit configured to generate an inversed dataline sensing enabling signal in response to a first dataline sensing enabling signal;
• a charge sync unit configured to discharge charges of the pair of local datalines at the precharging voltage level in response to the first dataline sensing enabling signal, the inversed dataline sensing enabling signal, and the data of the pair of local datalines;
• and
• a data sensing unit configured to transmit the data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

A method of operating a semiconductor memory device, the method comprising:

• precharging a pair of local datalines to a precharging voltage level in response to a precharging signal;
• detecting and amplifying memory cell data transmitted to a pair of bitlines;
• transmitting data of the pair of bitlines to the pair of local datalines in response to a column selecting signal;
• detecting and amplifying data of the pair of local datalines;
• discharging charges of the pair of local datalines at a precharging voltage level in response to a first dataline sensing enabling signal and the data of the pair of local datalines;
• and
• transmitting the data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

A method of operating a semiconductor memory device, the method comprising:

• precharging a pair of local datalines to a precharging voltage level in response to a precharging signal;
• detecting and amplifying memory cell data transmitted to a pair of bitlines;
• transmitting data of the pair of bitlines to the pair of local datalines in response to a column selecting signal;
• detecting and amplifying data of the pair of local datalines;
• discharging charges of the pair of local datalines at a precharging voltage level in response to a first dataline sensing enabling signal and an inversed dataline sensing enabling signal;
• and
• transmitting the data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.