Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits

A non-transitory machine-readable media having stored thereon instructions that when executed by a machine causes the machine to perform operations comprising:

• performing a first static timing analysis on a subset of data paths in a design specific netlist of an integrated circuit design in response to a process corner library and a general on chip variation de-rating factor, wherein the static timing analysis generates first path timing data for the subset of data paths in the design specific netlist;
• performing a statistical static timing analysis on the subset of data paths in the design specific netlist in response to a process sensitive delay library and a selected average yield for the integrated circuit design, wherein the statistical static timing analysis generates second path timing data for the subset of data paths in the design specific netlist;
• and
• determining one or more design-specific on-chip-variation (DS-OCV) de-rating factors in response to the first path timing data differing from the second path timing data, the one or more design-specific on chip variation de-rating factors to provide improved design specific timing results in a second static timing analysis of data paths in the design specific netlist.

A system for timing analysis of an integrated circuit design, the system comprising:

• a processor to execute instructions;
• and
• instructions stored in a storage device that when executed by the processor perform operations including
• performing a first static timing analysis on a subset of data paths in the design specific netlist in response to a process corner library and a general on chip variation de-rating factor, wherein the static timing analysis generates first path timing data for the subset of data paths in the design specific netlist;
• performing a statistical static timing analysis on the subset of data paths in the design specific netlist in response to a process sensitive delay library, wherein the statistical static timing analysis generates second path timing data for the subset of data paths in the design specific netlist;
• and
• calculating one or more design-specific on-chip-variation (DS-OCV) de-rating factors in response to the first path timing data and the second path timing data, the one or more design-specific on chip variation de-rating factors to provide improved design specific timing results in a second static timing analysis of data paths in the design specific netlist.