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US 8,331,138 B1Granted
Non-volatile electromechanical configuration bit array
AssigneeAgate Logic, Inc.
InventorsDavid Richard Trossen, Malcolm John Wing
Life of this patent
Estimating the term…
Abstract
A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.
Claims19
A memory cell consisting:
- a first electromechanical device having a first terminal, a second terminal, and a third terminal, the first terminal of the first electromechanical device connected to a first movable nanoscopic element, the third terminal of first electromechanical device connected to a common output node;
- a second electromechanical device having a first terminal, a second terminal, and a third terminal, the first terminal of the second electromechanical device connected to a second movable nanoscopic element, the third terminal of the second electromechanical device connected to the common output node, the first and second electromechanical devices operate to store one bit;
- a transistor having a first terminal, a second terminal, and a third terminal connected commonly to the third terminal of the first electromechanical device, the third terminal of the second electromechanical device, and the common output node;
- a first wordline extending in a first direction and connected to the first terminal of the first electromechanical device;
- a second wordline extending in a first direction and parallel to the first wordline, the second wordline connected to the first terminal of the second electromechanical device;
- a first bitline extending in a second direction, the first bit line connected to the second terminal of the first electromechanical device;
- a second bitline extending in a second direction and parallel to the first bitline, the second bitline connected to the second terminal of the electromechanical device;
- and
- a conductor extending in a second direction and parallel to the first and second bitlines, the conductor connected to the first terminal of the first transistor.
6 more elements
An array of memory cells, comprising:
- a plurality of memory cells, each memory cell consisting a first electromechanical device having a first terminal, a second terminal, and a third terminal, the first terminal of the first electromechanical device connected to a first movable nanoscopic element, the third terminal of first electromechanical device connected to a common output node;
- a second electromechanical device having a first terminal, a second terminal, and a third terminal, the first terminal of the second electromechanical device connected to a second movable nanoscopic element, the third terminal of the second electromechanical device connected to the common output node, the first and second electromechanical devices operate to store one bit;
- a transistor having a first terminal, a second terminal, and a third terminal connected commonly to the third terminal of the first electromechanical device, the third terminal of the second electromechanical device, and the common output node;
- a first wordline extending in a first direction and connected to the first terminal of the first electromechanical device;
- a second wordline extending in a first direction and parallel to the first wordline, the second wordline connected to the first terminal of the second electromechanical device;
- a first bitline extending in a second direction, the first bit line connected to the second terminal of the first electromechanical device;
- and
- a second bitline extending in a second direction, the second bit line connected to the second terminal of the second electromechanical device.
5 more elements
A memory cell, consisting:
- a first electromechanical device having a first terminal, a second terminal, and a third terminal, the third terminal of the first electromechanical device connected commonly to a first movable nanoscopic element and a common output node;
- a second electromechanical device having a first terminal, a second terminal, and a third terminal, the third terminal of the second electromechanical device connected commonly to a second movable nanoscopic element and the common output node, the first and second electromechanical devices operate to store one bit;
- a transistor having a first terminal, a second terminal, and a third terminal connected commonly to the third terminal of the first electromechanical device, the third terminal of the second electromechanical device, and the common output node;
- a first wordline extending in a first direction and connected to the first terminal of the first electromechanical device;
- a second wordline extending in a first direction and parallel to the first wordline, the second wordline connected to the first terminal of the second electromechanical device;
- a first bitline extending in a second direction, the first bit line connected to the second terminal of the first electromechanical device;
- and
- a second bitline extending in a second direction, the second bit line connected to the second terminal of the second electromechanical device.
5 more elements
A configuration bit memory cell, comprising:
- first and second carbon nanoscopic switching devices, each of the first and second carbon nanoscopic switching devices including a movable nanoscopic element, an attractor plate, and a release plate;
- first and second sources of potential of different values;
- a transistor having a first terminal connected to the first source, a second terminal connected to the second source, and a third terminal;
- a common output joining the attractor plate of the first carbon nanoscopic switching device, the attractor plate of the second carbon nanoscopic switching device, and the third terminal of the transistor;
- and
- connection circuitry to complete a first conductive path through one of the carbon nanoscopic switching devices and open a second the conductive path through the other of the carbon nanoscopic switching devices.
3 more elements
Dependencies are inferred from the claim text.