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US 8,331,128 B1Granted
Reconfigurable memory arrays having programmable impedance elements and corresponding methods
AssigneeAdesto Technologies Corporation
InventorsNarbeh Derhacobian, Shane Charles Hollmer
Life of this patent
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Abstract
A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.
Claims26
A memory device, comprising:
- a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions by configuration values corresponding to each portion, each portion being separately configurable for one of the data retention times;
- and
- configuration registers configured to store each configuration value, each configuration register including storage locations and a write path for receiving configuration values for storage.
A memory device comprising:
- a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions by configuration values corresponding to each portion, each portion being separately configurable for one of the data retention times;
- and
- a plurality of write circuits coupled to the memory cells, each write circuit configured to select between the data retention times in response to at least one of a plurality of configuration values.
A memory device comprising:
- a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions by configuration values corresponding to each portion, each portion being separately configurable for one of the data retention times;
- and
- an address translator configured to translate a first range of logical addresses into physical addresses of a first portion programmed to a first data retention time and translate a second range of logical addresses into physical addresses of a second portion programmed to a second data retention time different from the first data retention time.
An integrated circuit method, comprising:
- forming access circuits in an integrated circuit substrate, the access circuits configurable to program corresponding memory elements comprising a solid ion conductor between at least two different data retention times;
- and
- configuring at least two access circuits to program their corresponding memory elements to one of the data retention times with configuration information stored by the integrated circuit by writing configuration information to configuration registers on the integrated circuit.
A method, comprising:
- writing data values to different portions of a memory array with a write energy that varies according to a configuration value for each portion, the memory array including elements comprising a solid state ion conductor;
- and
- writing data values to different portions of a memory array includes selecting a write energy based on a comparison between a received address value and a configuration value.
Dependencies are inferred from the claim text.