Compilation model

A method to generate control system executable code, comprising:

• employing a processor executing computer executable instructions embodied on at least one non-transitory computer readable medium to perform operations comprising:
• receiving compiled code in a programming language;
• assembling the compiled code into an assembly code object in an intermediate language that is hardware processor independent;
• creating an intermediate language binary file from the assembly object code, wherein the intermediate language binary file is hardware processor independent;
• and
• creating a first target executable code program from the intermediate language binary file based on a first programmable logic controller definition for a first hardware processor and creating a second target executable code program from the intermediate language binary file based on a second programmable logic controller definition for a second hardware processor, wherein the first hardware processor is distinct from the second hardware processor, the first target executable code program is native assembler code executable by the first hardware processor but not by the second hardware processor, and the second target executable code program is native assembler code executable by the second hardware processor but not by the first hardware processor.

A non-transitory computer-readable medium having instructions stored thereon that, in response to execution, cause at least one device to perform operations to facilitate creating executable code for an industrial environment, the operations comprising:

• receiving compiled code in a programming language;
• assembling the compiled code into an assembly code object in an intermediate language that is hardware processor independent;
• creating an intermediate language binary file from the assembly object code, wherein the intermediate language binary file is hardware processor independent;
• and
• creating a first target executable code program from the intermediate language binary file based on a first programmable logic controller definition for a first hardware processor and creating a second target executable code program from the intermediate language binary file based on a second programmable logic controller definition for a second hardware processor, wherein the first hardware processor is distinct from the second hardware processor, the first target executable code program is native assembler code executable by the first hardware processor but not by the second hardware processor, and the second target executable code program is native assembler code executable by the second hardware processor but not by the first hardware processor.