US 8,325,751 B2Granted

Mixed hardware/software architecture and method for processing communications

AssigneeRealtek Semiconductor Corp.

InventorMing-Kang Liu

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Abstract

A method of implementing a scaleable architecture for a communications system considers the requirements of a particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs achievable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field. A system constructed in this fashion is highly gate efficient and cost effective, so that a multiport system can be put on single SOC integrated circuit.

Claims34

Dependent claims

A communication system comprising:

at least one communication port amongst a plurality of ports to receive data to be processed via a plurality of operation stages;
a hardware subsystem to perform a hardware operation associated with the received data;
a software subsystem to perform a software operation associated with the received data;
an operation determining logic to determine at least one of the operation stages to be performed by at least one of the hardware subsystem or the software subsystem, the operation determining logic configured to determine the operation stage to be performed based on a first, a second, and a third number of instructions per second (MIPs), or a first, a second, and a third number of gates or transistors or gates and transistors, or a first, a second, and a third number of number of MIPs per gates or MIPs per transistors or MIPS per gates and MIPS per transistors, or a first, a second, and a third number of instructions, or a first, a second, and a third amount of power consumption to perform the operation stage;
and
each of the plurality of ports having a clock rate amongst a plurality of clock rates respectively, wherein the communication system further includes an internal clock device for generating an internal clock, wherein the rate of the internal clock is faster than the rate of each of the clocks associated with the ports respectively.

3 more elements

A communication method comprising:

receiving data, in at least one communication port amongst a plurality of ports of a communication system, to be processed via a plurality of operation stages in the communication system, the communication system having a hardware subsystem to perform a hardware operation associated with the received data, the hardware subsystem being a hardware based unit, the communication system having a software subsystem to perform a software operation associated with the received data, the software subsystem being a software based unit, the software subsystem being different from the hardware subsystem;
determining, using an operation determining logic of the communication system, an operation stage of the plurality of operation stages to be performed by at least one of the hardware subsystem or the software subsystem, the determination based on one of more of
a first number of instructions per second (MIPs) required by the hardware subsystem to perform the operation stage, a second number of MIPs required by the software subsystem to perform the operation stage, and a third number of MIPs required by the combination of the hardware subsystem and the software system to perform the operation stage, or
a first number of gates or transistors or gates and transistors required by the hardware subsystem to perform the operation stage, a second number of gates or transistors or gates and transistors required by the software subsystem to perform the operation stage, and a third number of gates or transistors or gates and transistors required by the combination of the hardware subsystem and the software system to perform the operation stage, or
a first number of MIPs per gates or MIPS per transistors or MIPS per gates and MIPS per transistors required by the hardware subsystem to perform the operation stage, a second number of MIPs per gates or MIPS per transistors or MIPS per gates and MIPS per transistors required by the software subsystem to perform the operation stage, and a third number of number of MIPs per gates or MIPs per transistors or MIPS per gates and MIPS per transistors required by the combination of the hardware subsystem and the software system to perform the operation stage, or
a first number of instructions required by the hardware subsystem to perform the operation stage, a second number of instructions required by the software subsystem to perform the operation stage, and a third number of instructions required by the combination of the hardware subsystem and the software system to perform the operation stage, or
a first amount of power consumption required by the hardware subsystem to perform the operation stage, a second amount of power consumption required by the software subsystem to perform the operation stage, and a third amount of power consumption required by the combination of the hardware subsystem and the software system to perform the operation stage;
performing the operation stage on the data based on the determined result;
and
operating each of the plurality of ports including the at least one communication port having a clock rate amongst a plurality of clock rates respectively wherein the communication system uses an internal clock device for generating an internal clock, wherein the rate of the internal clock is faster than the rate of each of the clocks associated with the ports respectively.

7 more elements

A communication method comprising:

receiving data, in at least one communication port amongst a plurality of ports of a communication system, to be processed via a plurality of operation stages in the communication system, the communication system having a hardware subsystem to perform a hardware operation associated with the received data, the hardware subsystem being a hardware based unit, the communication system having a software subsystem to perform a software operation associated with the received data, the software subsystem being a software based unit, the software subsystem being different from the hardware subsystem;
determining, using an operation determining logic of the communication system, an operation stage of the plurality of operation stages to be performed by at least one of the hardware subsystem or the software subsystem, the determination based on one of more of
a first number of instructions per second (MIPs) to perform the operation stage, a second number of MIPs to perform the operation stage and a third number of MIPs to perform the operation stage, or
a first number of gates or transistors or gates and transistors to perform the operation stage, a second number of gates or transistors or gates and transistors to perform the operation stage, and a third number of gates or transistors or gates and transistors to perform the operation stage, or
a first number of MIPs per gates or MIPS per transistors or MIPS per gates and MIPS per transistors to perform the operation stage, a second number of MIPs per gates or MIPS per transistors or MIPS per gates and MIPS per transistors to perform the operation stage, and a third number of number of MIPs per gates or MIPs per transistors or MIPS per gates and MIPS per transistors to perform the operation stage, or
a first number of instructions to perform the operation stage, a second number of instructions to perform the operation stage, and a third number of instructions to perform the operation stage, or
a first amount of power consumption to perform the operation stage, a second amount of power consumption to perform the operation stage, and a third amount of power consumption to perform the operation stage;
performing the operation stage on the data based on the determined result, wherein the step of determining also determines the operation stage based on a first time period required by the hardware subsystem to perform the operation stage, a second time period required by the software subsystem to perform the operation stage, and a third time period required by the combination of the hardware subsystem and the software system to perform the operation stage;
and
operating each of the plurality of ports including the at least one communication port having a clock rate amongst a plurality of clock rates respectively wherein the communication system uses an internal clock device for generating an internal clock, wherein the rate of the internal clock is faster than the rate of each of the clocks associated with the ports respectively.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/986,502Filed 10 Nov 2004 · division
Priority: 1 Mar 2000
Published: US 2005/0071800 A131 Mar 2005
Granted: 4 Dec 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H04L 12/2856
Wide area networks, e.g. public data networks: access arrangements, e.g. Internet access
G06F 9/3867
Concurrent instruction execution, e.g. pipeline or look ahead: using instruction pipelines
H04L 1/0043
Arrangements at the transmitter end: realisations of complexity reduction techniques, e.g. use of look-up tables
H04L 1/0052
Arrangements at the receiver end: realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables

Family

Application60/185,964Us provisional application · filed 1 Mar 2000
Application09/797,793Parent of this division · filed 1 Mar 2001
US 2005/0071800 A1Pre-grant publication · published 31 Mar 2005
US 6,839,889 B2Parent of this division
US 2001/0047465 A1Published application
US 8,325,751 B2This patent

From the US filing history. Foreign family members aren’t listed.