US 8,324,032 B2Granted

Method of manufacturing a semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsHideto Ohnuma, Ichiro Uehara

Life of this patent

Estimating the term…

Loading patent…

Abstract

Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing, the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

Claims19

Dependent claims

A method of manufacturing a semiconductor device comprising the steps of:

forming a conductive film over a first semiconductor and a second semiconductor with an insulating film therebetween;
forming a rectangular shape first resist pattern on the conductive film over the first semiconductor, and forming a second resist pattern on the conductive film over the second semiconductor, wherein a thickness of an edge portion of the resist pattern is smaller than thickness of a middle portion of the resist pattern;
forming a rectangular shape first gate electrode over the first semiconductor by a first dry etching using the first resist pattern, and forming a second gate electrode by the first dry etching using the second resist pattern over the second semiconductor, wherein a thickness of an edge portion of the second gate electrode is smaller than a thickness of a middle portion of the second gate electrode;
introducing an impurity element into the first semiconductor with the first gate electrode as a mask to form a first impurity region in the first semiconductor, wherein the first impurity region is not overlapped with the first gate electrode, and introducing an impurity element into the second semiconductor with the second gate electrode as a mask to form a second and a third impurity regions in the second semiconductor, wherein the second impurity region is not overlapped with the second gate electrode and the third impurity region is overlapped with the edge portion of the second gate electrode;
and
making the edge portion of the second gate electrode recede by a second dry etching.

3 more elements

A method of manufacturing a semiconductor device comprising the steps of:

forming a conductive film over a first semiconductor and a second semiconductor with an insulating film therebetween;
forming a first resist pattern on the conductive film over the first semiconductor and a second resist pattern on the conductive film over the second semiconductor, wherein a thickness of an edge portion of the first resist pattern and a second thickness of an edge portion of the second resist pattern are smaller than thickness of a middle portion each of the first and the second resist patterns;
forming a first gate electrode by a first dry etching using the first resist pattern, wherein a first thickness of an edge portion of the first gate electrode is smaller than a thickness of a middle portion of the first gate electrode, and forming a second gate electrode by the first dry etching using the second resist pattern, wherein a second thickness of an edge portion of the second gate electrode is smaller than a thickness of a middle portion of the second gate electrode;
removing the first and the second resist patterns;
introducing an impurity element into the first semiconductor with the first gate electrode as a mask to form a first impurity region and a second impurity region in the first semiconductor, wherein the first impurity region is not overlapped with the first gate electrode and the second impurity region is overlapped with the edge portion of the first gate electrode, and introducing the impurity element into the second semiconductor with the second gate electrode as a mask to form a third impurity region and a fourth impurity region in the second semiconductor, wherein the third impurity region is not overlapped with the second gate electrode and the second impurity region is overlapped with the edge portion of the second gate electrode;
making the edge portions of the first and the second gate electrodes recede by a second dry etching;
forming a third resist pattern over the first gate electrode, wherein the second gate electrode is exposed from the third resist pattern;
and
making the edge portion of the second gate electrode recede by a third dry etching.

6 more elements

A method of manufacturing a semiconductor device comprising the steps of:

forming a conductive film over a semiconductor with an insulating film therebetween;
forming a rectangular shape first resist pattern on the conductive film, and forming a second resist pattern on the conductive film, wherein a thickness of an edge portion of the second resist pattern is smaller than thickness of a middle portion of the second resist pattern;
forming a rectangular shape first gate electrode by a first dry etching using the first resist pattern, and forming a second gate electrode by the first dry etching using the second resist pattern, wherein a thickness of an edge portion of the second gate electrode is smaller than a thickness of a middle portion of the second gate electrode;
removing the first and the second resist patterns;
introducing an impurity element into the semiconductor with the first gate electrode as a mask to form a first impurity region in the semiconductor, wherein the first impurity region is not overlapped with the first gate electrode, and introducing the impurity element into the semiconductor with the second gate electrode as a mask to form a second and a third impurity regions in the semiconductor, wherein the second impurity region is not overlapped with the second gate electrode and the third impurity region is overlapped with the edge portion of the second gate electrode;
and
making the edge portion of the second gate electrode recede by a second dry etching.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/152,492Filed 3 Jun 2011 · continuation
Priority: JP 2000-24486011 Aug 2000
Published: US 2011/0294266 A11 Dec 2011
Granted: 4 Dec 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 86/0231
Of multiple TFTs: using masks, e.g. half-tone masks
H10D 30/0229
Having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped…
H10D 30/0314
Characterised by the gate electrodes: of lateral top-gate TFTs comprising only a single gate
H10D 30/0321
Of thin-film transistors [TFT]: comprising silicon, e.g. amorphous silicon or polysilicon

Family

Application09/925,512Parent of this division · filed 10 Aug 2001
Application11/754,484Parent of this continuation · filed 29 May 2007
US 7,223,643 B2Parent of this division · filed 29 May 2007
Application11/969,247Parent of this continuation · filed 4 Jan 2008
US 7,316,946 B2Parent of this continuation · filed 8 Jan 2008
Application12/823,175Parent of this continuation · filed 25 Jun 2010
US 7,745,271 B2Parent of this continuation · filed 29 Jun 2010
US 2011/0294266 A1Pre-grant publication · published 1 Dec 2011
US 7,955,912 B2Parent of this continuation
Application11/754,484Parent of this division
US 2002/0025591 A1Published application
US 2007/0218604 A1Published application
US 2008/0119024 A1Published application
US 2010/0261320 A1Published application
US 8,324,032 B2This patent

From the US filing history. Foreign family members aren’t listed.