NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor
AssigneeCrossbar, Inc.
InventorHagop Nazarian
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in series with a gate of the first transistor. The non-volatile memory device further includes a first bit line coupled to a drain of the first select transistor and a plurality of word lines. Each word line is coupled to one of the first memory cells.
Claims26
A non-volatile memory device, comprising:
- a first select transistor;
- a second select transistor;
- a first string of first memory cells provided between the first and second select transistors, each first memory cell having a first resistive memory cell and a first transistor, the first resistive memory cell being in series with a gate of the first transistor;
- a first bit line coupled to a drain of the first select transistor;
- and
- a plurality of word lines, each word line being coupled to one of the first memory cells.
A non-volatile memory device, comprising:
- a first string of first memory cells, each first memory cell having a first resistive memory cell and a first transistor, the first resistive memory cell being in series with a gate of the first transistor;
- a first bit line coupled to the first string;
- a second string of second memory cells, each second memory cell having a second resistive memory cell and a second transistor, the second resistive memory cell being in series with a gate of the second transistor;
- a second bit line coupled to the second sting;
- and
- a plurality of word lines, each word line being coupled to one of the first memory cells in the first string and one of the second memory cells in the second string.
The non-volatile memory device 23, wherein each resistive memory cell is connected in series to a gate of the corresponding transistor.
The non-volatile memory device 23, wherein each resistive memory cell is configured to store more than a single bit of information.
Dependencies are inferred from the claim text.