Power efficient push-pull buffer circuit, system, and method for high frequency signals

An electronic system, comprising:

• a signal generation circuit operable to generate an input signal;
• a buffer circuit coupled to the signal generation circuit to receive the input signal, the buffer circuit comprising:
• a biasing circuit operable to generate first and second biasing signals;
• a capacitive network including an input adapted to receive the input signal and the capacitive network operable responsive to the input signal to generate first and second bootstrapped signals;
• and
• a push-pull stage including first and second control inputs and an output, the push-pull stage being coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively, the push-pull stage operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals;
• wherein the biasing circuit comprises elements sized to bias the push-pull stage between a turn-on threshold and a fully on state;
• and
• electronic circuitry coupled to the output of the push-pull stage of the buffer circuit to receive the buffered output signal.

A method of utilizing a push-pull stage to generate a buffered output signal, the push-pull stage including first and second control inputs and an output, and method comprising:

• applying first and second biasing signals to the first and second control inputs, the biasing signals having a magnitude suited to set the push-pull stage between slightly on and fully on;
• generating an input signal;
• generating first and second bootstrapped signals responsive to the input signal;
• and
• applying the first and second bootstrapped signal on the first and second control inputs to cause the push-pull stage to generate the buffered output signal on the output responsive to the first and second bootstrapped signals.

A buffer circuit, comprising:

• a biasing circuit operable to generate first and second biasing signals;
• a capacitive network including an input adapted to receive an input signal and the capacitive network operable responsive to the input signal to generate first and second bootstrapped signals;
• and
• a push-pull stage including first and second control inputs and an output, the push-pull stage being coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively, the push-pull stage operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals;
• wherein the biasing circuit comprises elements sized to bias the push-pull stage between a turn-off threshold and a fully on state.

A buffer circuit, comprising:

• a biasing circuit operable to generate first and second biasing signals;
• a capacitive network including an input adapted to receive an input signal and the capacitive network operable responsive to the input signal to generate first and second bootstrapped signals;
• and
• a push-pull stage including first and second control inputs and an output, the push-pull stage being coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively, the push-pull stage operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals;
• wherein the biasing circuit comprises elements sized to bias the push-pull stage between a class B mode of operation and a class AB mode of operation.