Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTakayuki Iwai, Shuso Fujii, Shinji Miyano
Life of this patent
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Abstract
A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.
Claims18
A semiconductor memory device configured to selectively adopt a twin-cell configuration and a single-cell configuration, comprising:
- a memory cell array comprising a plurality of memory cells arranged at intersections of word-lines and bit-lines;
- a sense amplifier circuit configured to sense and amplify a signal read from the memory cells;
- a write circuit configured to write, according to first data held in a first memory cell of the memory cells, second data corresponding to the first data to a second memory cell different from the first memory cell as second data corresponding to the first data, when the twin-cell configuration is selected, the second memory cell being connected to a sense amplifier circuit different from that connected to the first memory cell;
- a data latch circuit configured to hold data read from the first memory cell;
- a logic operation circuit configured to perform a logic operation using data read from the second memory cell and data held in the data latch circuit as input values, and output third data as an operation value;
- and
- a write-back circuit configured to write the third data back to the first memory cell.
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged at intersections of word-lines and bit-lines, each memory cell storing data by holding a charge in a capacitor;
- a sense amplifier circuit configured to sense and amplify a signal read from the memory cell;
- a read amplifier configured to further amplify an amplification signal from the sense amplifier circuit, and outputting read data;
- a write circuit configured to write, in a normal operation, write data to the memory cell, the write data being to be written to the memory cell, and write, in a twin-cell configuration in which two memory cells hold the same data, a first data read from a first memory cell of the memory cells to a second memory cell different from the first memory cell as a second data corresponding to the first data, the second memory cell being connected to a sense amplifier circuit different from that connected to the first memory cell;
- and
- a logic operation circuit configured to perform a logic operation using data read from the second memory cell and data read from the first memory cell as input values, and output third data as an operation value;
- the write circuit writing the third data back to the first memory cell.
Dependencies are inferred from the claim text.