# US 8,305,808 B2 · Low-voltage EEPROM array

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- Number: US 8,305,808 B2
- Document ID: US8305808B2
- Status: Granted
- Kind: B2
- Application number: 12/854,989
- Filed: 2010-08-12
- Published: 2012-02-16
- Granted: 2012-11-06
- Earliest claimed: 2010-08-12
- Assignees: Yield Microelectronics Corp.
- Inventors: Hsin Chang Lin; Chia-Hao Tai; Yang-Sen Yen; Ming-Tsang Yang; Ya-Ting Fan
- Web page: https://patentgrep.com/patent/US8305808B2

## CPC

- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.

## Claims

### Claim 1

A low-voltage electrically erasable programmable read only memory array, comprising
a plurality of parallel bit lines, including a first bit line;
a plurality of parallel word lines extending substantially perpendicular to said bit lines, including a first word line and a second word line;
a plurality of parallel common source lines parallel to said word lines, including a first common source line and a second common source line; and
a plurality of sub-memory arrays each connecting with one said bit line, two said word lines and two said common source lines, and arranged between two said common source lines, wherein each said sub-memory array includes:
a first memory cell connecting with said first bit line, said first common source line and said first word line; and
a second memory cell connecting with said first bit line and having a common connection point at said first bit line with said first memory cell, and connecting with said second common source line and said second word line, wherein said first memory cell and said second memory cell are symmetrical and arranged between said first common source line and said second common source line,
each of said first and second memory cells having a field effect transistor formed in a substrate or a well,
wherein said first and second memory cells of said plurality of sub-arrays are programmably separated into at least one selected memory cell connected to a respective bit line, a respective word line, and a respective common source line, a plurality of parity-bit memory cells connected with said respective bit line, and disconnected from said respective common source line, a plurality of parity-word memory cells connected with said respective word line, and a plurality of unselected memory cells,
wherein, when each of said first memory cell and said second memory cell has an n-type field effect transistor formed in p-type substrate or a p-type well,
a substrate voltage Vsubp is a lied to said p-type substrate or said p-type well of said at least one selected memory cell,
first bit voltage Vb1, first word voltage Vw1, and a first common source voltage VS1 are applied to said respective bit line, said respective word line and said respective common source line, respectively, connected to said selected memory cell,
a second word voltage Vw2 and a second common source voltage VS2 are applied to word lines and common source lines respectively, connected to said plurality parity-bit memory cells, respectively,
a second bit voltage Vb2 and said first common source voltage VS1 are applied to bit lines and common source lines, respectively, connected to said plurality of parity-word memory cells,
said second bit voltage Vb2, said second word voltage Vw2, and said second common source voltage VS2 are applied to bit lines, word lines and common source lines, respectively, connected to said plurality of unselected memory cells,
wherein said read only memory array operates in a “write” mode and in an “erase” mode,
wherein in the “write” mode:
said Vb2 is floating, said Vsubp is grounded, Vb1>VS2, Vw1>VS1, Vb1>VS10, Vb1>Vw2>0, Vb1>VS2>0, and
wherein in the “erase” mode:
said VS1 is grounded, said Vsubp is grounded, said Vb2 is floating, Vb1>Vw2>Vw1≧0, and Vb2>VS2>Vw1≧0; and
wherein when each of said first memory cell and said second memory cell has a p-type field effect transistor formed in an n-type substrate or an n-type well,
a substrate voltage Vsubn is applied to said n-type substrate or said n-type well of said at least one selected memory cell,
a first bit voltage Vb1, a first word voltage Vw1, and a first common source voltage VS1 are applied to said bit line, said word line, and said common source line respectively, connected to said at least one selected memory cell,
a second word voltage Vw2 and a second common source voltage VS2 are applied to said word lines and said common source lines, respectively, connected to said parity-bit memory cells,
a second bit voltage Vb2 and said first common source voltage VS1 are applied to said bit lines and said common source lines, respectively, connected to said parity-word memory cells,
said second bit voltage Vb2, said second word voltage Vw2 and said second common source voltage VS2 are applied to said bit lines, said word lines, and said common source lines, respectively, connected to said unselected memory cells,
wherein in the “write” mode: said Vb2 is floating, Vsubn>VS1>Vb1, Vsubn>VS1>Vw1, Vsubn>VS2>Vb1, Vsubn>Vw2>Vb1, and
wherein in the “erase” mode:
said Vb2 is floating, Vsubn=VS1≧Vw1>Vb1, Vsubn>VS2>Vb1, and Vsubn>Vw2>Vb1.

### Claim 2 (depends on 1)

The low-voltage electrically erasable programmable read only memory array according to claim 1, wherein said field effect transistor of said first memory cell includes:
a floating gate, wherein a drain of said field effect transistor connects with said first bit line to share said common connection point with said second memory cell, and wherein a source of said field effect transistor connects with said first common source line; and
a capacitor, wherein one terminal of said capacitor connects with said floating gate, and wherein another terminal of said capacitor connects with said first word line to receive a bias voltage of said first word line, and wherein said field effect transistor receives bias voltages of said first bit line and said first common source line to write data to said floating gate or erase data of said floating gate.

### Claim 3 (depends on 2)

The low-voltage electrically erasable programmable read only memory array according to claim 2, wherein said field effect transistor is an n-type field effect transistor or a p-type field effect transistor.

### Claim 4 (depends on 2)

The low-voltage electrically erasable programmable read only memory array according to claim 2, wherein said field effect transistor is formed in a semiconductor substrate, and wherein an oxide layer and a control gate are sequentially formed above said floating gate, and wherein said control gate, said oxide layer and said floating gate form said capacitor, and wherein said floating gate and said control gate are made of a polysilicon material.

### Claim 5 (depends on 1)

The low-voltage electrically erasable programmable read only memory array according to claim 1, wherein said field effect transistor of said second memory cell includes:
a floating gate, wherein a drain of said field effect transistor connects with said first bit line to share said common connection point with said first memory cell, and wherein a source of said field effect transistor connects with said second common source line; and
a capacitor, wherein one terminal of said capacitor connects with said floating gate, and wherein another terminal of said capacitor connects with said second word line to receive a bias voltage of said second word line, and wherein said field effect transistor receives bias voltages of said first bit line and said second common source line to write data to said floating gate or erase data of said floating gate.

### Claim 6 (depends on 5)

The low-voltage electrically erasable programmable read only memory array according to claim 5, wherein said field effect transistor is an n-type field effect transistor or a p-type field effect transistor.

### Claim 7 (depends on 5)

The low-voltage electrically erasable programmable read only memory array according to claim 5, wherein said field effect transistor is formed in a semiconductor substrate, and wherein an oxide layer and a control gate are sequentially formed above said floating gate, and wherein said control gate, said oxide layer and said floating gate form said capacitor, and wherein said floating gate and said control gate are made of a polysilicon material.